Design And Research Of High Frame Rate Video System's Key Technology

High frame rate video is playing a critical role in security monitoring,industrial production,military reconnaissance and other fields,but the technology research in this field is underdeveloped in the domestic.Therefore,it is very necessary to study the high frame rate system.We will mainly focus on research on the key technologies of the high frame rate camera and its implementation.According to the KAI0340 CCD(Charge Coupled Device)image sensor of Kodak Company,we will cover the following issues in this paper,including the method to design and implement the timing logic and high speed driving circuits,the method to design the high-speed analog-to-digital converter circuit and the high-speed data receive circuit in FPGA,the method to choose the data compression algorithm to reduce the data volumn and the method to realize the high frame rate system.The main contents are as follows:High frame rate video system mainly includes three parts,high frame rate video system hardware design,high-speed transmission interface design and lossless compression algorithm design.High frame rate video system hardware design includes power module design,drive timing module design,analog-to-digital conversion module design.Power module is mainly responsible for the realization of the various power voltages to meet the requirement of the system.Drive timing generation module,including FPGA timing logic and high-speed drive circuit.Analog-to-digital conversion module conducts the analog-to-digital converter AD9928 peripheral hardware circuit design and its associated register configuration.High-speed transmission interface circuit design module,including transmission of data,data processing and control between cameras with the Personal Computer(PC).The system uses Camera Link interface to transmit the image data.The data processing part mainly includes data string concatenation,synchronization word extraction,and timing constraint.RS422 serial port is applied to meet the control requirements of the configuration of the analog-to-digital conversion chip,the image sensor chip and the registers' value in the FPGA.To make full use of the efficient data clustering ability of BWT transform and the better compression ability of LZW algorithm for the same continuous segment data,a data compression method based on BWT(Burrows-Wheeler Transfer)and LZW(Lemple-Ziv-Welch)coding is proposed in this thesis to reduce the data volumn and to improve the channel transmission efficiency.The compression algorithm is simulated and implemented both on MATLAB and on FPGA platform.The experimental results conducted on the realized camera show that the design and implementation scheme proposed in this paper is feasible.