Research And Design Of Radiation Hardened SRAM

With the progress of the integrated circuit manufacturing process,the scaling down of the feature size,the reducing of the working voltage and the improvement of working frequency,the influence of various radiation effect on the semiconductor device is becoming more and more serious.Static Random Access Memory(SRAM)because of its fast speed and low power consumption,has been widely applied in the aerospace field as the cache.However,the reliability of SRAM is seriously influenced by a large number of high energy particles in the space environment,which poses a great threat to the normal operation of the various spacecraft.Therefore,there is great significance to study the radiation hardened technology of SRAM.Based on the study of generation mechanism of single event effects and the study of the existing reinforcement technology,this paper designs a newly radiation hardened storage cell,Delay Self Restoring Logic(DSRL),which has the hardening ability to Single Event Upset(SEU),Single Event Transient(SET)and Single Event Multiple Node Upset(SEMNU)simultaneously.Then a radiation hardened SRAM with the size of 4Kbit is designed by the method of full custom.The main work of this paper is as follows:1.The origin of space radiation particles is studied.Then we analyze the mechanism of SEU,SET and SEMNU in detail,and sum up the common reinforcement technology and its deficiencies.2.In this paper,a new radiation hardened DSRL storage cell,based on SRL structure,using separately design of reading and writing,and adding special delay unit is proposed.Not only is this storage cell immune to SEU in the whole state,but also it can filter out the SET less than 1ns pulse during the process of reading and writing,and has good hardening effect to SEMNU.The detailed theoretical calculations of the parameters of DSRL cell transistor is made,the simulation results show that it meet the design requirements.3.Peripheral circuit matching the DSRL cell is designed and corresponding reinforcement is made.For example,filter unit is added to decoder in order to hardening the SET pulse.The sensitive amplifier is improved to make it more sensitive and reliable.The layout of the storage cell is made of hardening design,through the method of widening the distance between the sensitive nodes of SRAM,and adding protecting ring on NMOS and PMOS tube respectively,which make a further strengthening to the SEMNU.Finally,schematic design and layout design of the whole SRAM is carried out by the method of full custom.4.AMS software is used to build the digital-analog hybrid simulation platform to complete the functional verification of the designed SRAM.The single event effect model and the evaluation system are constructed,and the parasitic parameters are extracted.The fully post simulation verification is made on the hardening effect of the DSRL cell.