A Low Voltage SAR ADC Based On Voltage Controlled Delay Line And Bypass Logic

With the development of portable,wearable and biomedical equipment,it has a higher and higher requirement for wireless sensor.These sensors need to work on for long time.They collect data from human body or external environment and send them to DSP system.As a combiner for analog signal and digital signal,ADC is the most important part in wireless sensor.These ADCs have moderate working frequency from100 KHz to 1MHz,and moderate precision from 10 bit to 12 bit.The sensors are powered by battery or energy collecting system,and hoped to work as long as possible without service,which means ADCs must working in low voltage and containing low power.Aiming at these requirement,this paper propose a low power high energy efficient 10 bit SAR ADC in 65 nm CMOS technology.Firstly,this paper propose a new type of voltage controlled delay line(VCDL)comparator to avoid long judge time and high power proportion in conventional voltage domain comparator.This new VCDL contains two accuracy by using different number of delay stages.Besides,it fold the stages to avoid gate capacitors in MOSFET affecting DAC capacitor array.Secondly,aiming at low frequency biological signals,this propose a bypass control logic in time domain to skip some unnecessary bits conversion.And propose a time domain window detection module to decide whether the bypass logic can be performed.This module is based on the new VCDL and time domain bypass control logic.Thirdly,to solve PVT variation in detection module and offset voltage between two mode VCDL,this paper propose a calibration method in reset period.The calibration is performed in delay cells in detection module.Based on technique above-mentioned,this paper designs a 10 bit SAR ADC working on 0.5V voltage.It achieves 625KS/sample sampling frequency,72.85 dB SFDR,61.437 dB SNDR,9.93 bit ENOB,0.917 uW power dissipation and1.503fJ/Conv.-s FoM.