Massive Channel Receiver Design And Implementation

In recent decades,wireless communications science and technology is rapidly developed,affecting all aspects of human life.With the rise of IOT(Internet of Things)technology,the application of wireless communication technology in IOT gets great attention.In typical IOT applications,such as smart meters,researchers face the challenges of uniformly receiving and demodulating signals transmitted by massive numbers of sensors.For those applications,the time at which the transmitting nodes send messages is random,and the carriers on which every node located are different.The central node simultaneously detects all the sub-channels and processes the wireless signals of all transmitting nodes in parallel.Traditional wireless receiver designs have to be assigned independent processing modules for every transmitting node,such as DDC(Digital Down Converter),carrier synchronization,timing synchronization and other high computational complexity modules,to achieve parallel processing capabilities.But in face of hundreds of transmitting nodes,the problem of resource consumptions and design complexities would become very tricky.This paper proposed a massive channel parallel wireless communication receiver design that can simultaneously receive and demodulate the transmission signals of massive monitoring nodes in the IOT network.A new type of IOT protocol which defines hundreds of transmitting nodes sending messages to one central node is considered,that is,a large number of transmitters located on different subcarriers randomly send messages to the same central receiver,and the center receiver should be able to process all the signals simultaneously.Based on the design requirements,this paper presents an efficient and feasible parallel receiver design from the aspects of algorithm and parallel receiving system structure.Finally,the parallel receiver design is verified based on Xilinx FPGA(FieldProgrammable Gate Array)hardware platform and gets reliable performance.This paper proposes a new efficient parallel DDC algorithm based on FFT(Fast Fourier Transform),and analyzes the implementation strategies of function modules in the receiving link,so system parallel processing capacities are obtained.An innovative embedded parallel receiver system architecture based on microcontroller is proposed too.Both theoretical analysis and simulation verification validate feasibility and good performance of the new massive channel receiver design.Finally,we realized the receiver design on hardware platform,tested the receiver sensitivity in the real environment and the receiver sensitivity results are in good agreement with theory.