Research And Design On Single Channel High Speed Low Power SAR ADC

In analog-to-digital converters(ADCs)world,successive-approximation register(SAR)ADCs have their unique position.Due to its’ own structure,SAR ADC need many cycles to achieve one complete quantization which lead to SAR ADC slower than Flash ADC and pipeline ADC.In contrast to flash and pipeline architectures,successive-approximation register ADC is simple,energy-efficient,and well-adapted in advanced processes.In recent years,analog engineers and researchers in university proposed kinds of novel techniques and structures to improve sampling rate base of SAR ADCs’ characteristics.These progress make SAR ADC suit for medium resolution hundreds of MS/s analog-to-digital converters are demanded in applications such as wireless communication systems,hard disk read channels,and Ethernet networks.This thesis focuses on the design of single channel high speed low power successive-approximation register ADC.Based on the beheaviral modeling and analysis of practical issues and schematic problems in the SAR ADC design,this thesis presents a 10 bits 336MS/s SAR ADC in a 40 nm CMOS at 1.2V supply.To enhancing convert speed of SAR ADC,this thesis proposed fast controlled logic techniques.Also optimized digital-to-analog capacitors(DAC)arrary are investigated for decresing chip area and power,finally the unit capacitance is determined at 1fF.By carefully designing and optimizing our system architechture and circuit implementaion,the chip was successfully taped out and achieved a measurement result.The measured results show the peak SNDR and SFDR is 56.79 dB and 72.8dB,and peak ENOB is 9.14 at 1.2V supply when sampling clock is 336MS/s and sinewave signal frequency is 11.171 MHz.