The Design Of Low Power Accelerating System For Intelligent Hardware

Recently,with the rapid development of modern technology,the development electronic product gradually transforming into the development of intelligent hardware since the emergence of smartphones.Intelligent hardware,combining software and hardware,redevelopming and adding intelligent features,improves the traditional equipment.Intelligent hardware has applications in a wide range of fields,including modern electronic equipment,e.g.watches,televisions,etc.,and traditional equipment,e.g.,door lock,car,house,etc.While the problem of battery life becomes acute as the development of intelligent hardware.It has been a research hotspot how to improve the power of intelligent hardware with good performance.The main contents of this thesis include the following.(1)Building a SoC(System on Chip)system architecture for applications of intelligent hardware by using RISC-V core proposed by UC Berkeley as CPU of the system because of its high performance and efficiency as well as low power.This SoC system uses AXI bus of AMBA 4.0 as on-chip bus,adopts independent instruction and data SRAM,and includes various peripheral interfaces.This thesis designs the architecture of this SoC system,simulates this design,and verifies it on FPGA hardware platform.The verification of the designed system by FPGA is completes on zedboard and HAPs.Results show that the system is up to 100 MHZ on frequency with only 20.071 mW dynamic power in total.(2)Designing an accelerator system for intelligent hardware based on AHB high-speed bus of AMBA 4.0.A 512 MB LP DDR memory block is mounted on the system.Besides,the system includes a camera OV7670 control module,an EMMC control module,and an ANN module.(3)Implementing the transform of AXI-to-AHB and the integration of big core SoC system and AHB accelerator system.Implementing UART communication lines connecting systems of big core and small core,and their interaction.The SoC system of big core has high capacity for processing complex applications,which the system of small core has low capacity to only processing simple applications.All modules have high speeds on AHB accelerator system,processing specific complex algorithms,or extending the system.Systems of big core and small core can be applied either interdependencely or independently.AHB accelerator system is controlled by the big core SoC system.The design of this thesis is come from a project of the research group,and the project has reached the final stage.The whole system is consisted of three systems: big core and small core systems,as well as AHB accelerator system.Both of the big core and small core systems can be sleeped by RI5 CY when they are idle to reduce the power consumption.The tasks are allocated to the systems of big core and small core according to their complexes,for using resources efficiently to reduce energy consumption.The three systems can be exploited either interdependencely or independently to reduce energy consumed by the whole system.