The Verification Of EMMC Controller Module Based On UVM

The rapid development of modern Integrated Circuit(IC)constantly increases the design level and the system complexity of System on Chip(SoC),and the increases of design level and complexity of the system greatly brings more workload for verification.Verification takes up about50% to 80% of the time and resources which SoC design work spends.The verification efficiency will directly affect the performance index and design cycle of the chip,and finding an advanced and effective verification method is the key to design SoC chip successfully.Universal Verification Methodologhy(UVM)inherits the advantages of Verification Methodology Manual(VMM)and Open Verification Methodology(OVM).Besides it overcomes the shortcomings of both and currently has the best compatibility and the most advanced working mechanism.The UVM represents the development direction of the verification methodology.Relying on design project for solid state disk’s control chip using embedded Muti Media Card(eMMC),this paper mainly studies UVM verification methodology.This paper conducts module-level validation and simulation for eMMC controller module which can be reused systematically in solid state hard disk.Based on comprehensive analysis on the structure,function and interface of eMMC controller module,this paper uses UVM verification methodology to develop a verification program,and find test points,and determine the structure of UVM verification platform.Besides this paper specifically implements every component of UVM verification platform using System Verilog language,and successfully set up UVM verification platform of the eMMC controller module.After building the verification platform,this paper invokes all kinds of test case with stochastic constraints to verify the full range of function of the eMMC controller module.Then this paper conducts analysis and comparison on the test results to find design loopholes of eMMC controller and ensure the validity of design of controller module eMMC.Code coverage rate of this validation simulation reaches 95% and the function coverage rate reaches 96%.The export conditions of verification are satisfied.It shows that the built verification platform is sophisticated,and we achieve the purpose of verification and improve the efficiency of the verification.This verification platform can be reused in a variety of solid-state equipment master chip verification platform,and it has high portability.This experiment is very successful.At the same time,it fully proves that the UVM verification methodology with high flexibility and reusability is the most important part of the present verification.