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FPGA-Based Hign-Speed Network Interface Logic Implementation

Posted on:2015-03-20Degree:MasterType:Thesis
Country:ChinaCandidate:D YaoFull Text:PDF
GTID:2348330518472959Subject:Underwater Acoustics
Abstract/Summary:PDF Full Text Request
Multi-beam imaging sonar system can be capable of efficiently detecting the seafloor landform and real-time high-precision imaging underwater detecting imaging equipment. To achieve the above functions, the system needs to real-time transport a large amounts of collected data, long-distance and high-speed transmission of data has become an urgent demand for imaging sonar systems. The paper studies the implementation of high-speed network interfaces and accomplishes the design and implementation of the software and hardware.The core of the designed system is the high-speed transmission of large amounts of data,to meet the requirements of high-speed transmission, designed the Gigabit Ethernet transmission system based on FPGA. To ensure the modules can be independently and high-speed running in the system by using the capability of FPGA parallel processing, use the Gigabit Ethernet technology to increase transmission bandwidth, solve the problem of high-speed transmission. According to the demanded indicators of the system and taking into account the difficulty of development and the factors of the cycle and costing of development,choose a reasonable peripheral chips and implementation. Use Altium Designer to complete the design of schematic, we can achieve the best layout based on the criteria of electromagnetic compatibility and signal integrity, complete the PCB design. Designing the UDP / IP protocol stack and other modules uses the hardware description languages. Use SOPC tools to build the hardware platform, use the Nios Ⅱ soft-core as the core of SOPC system, the design of the processor code is completed by using Nios Ⅱ Eclipse software. all the timing simulation and functional verification of the FPGA control logic is completed by using the Modelsim software.Finally, after accomplishing the whole Gigabit Ethernet system design, to verify that the performance of the system if meets the requirements of stability and the rate of transmission or not, i have repeatedly verified and tested the system for a long time, in the laboratory environment. The transmission speed of the system can stably run at 410Mbps and have no phenomenon of the losing packet and erring packet and so on, meeting the design requirements, achieving the desired design goals. Summarizing all the work of the paper,analyzing the tested results. Introducing the proposed ways of improving the transmission speed of Ethernet, Laid a solid foundation for subsequent practical application.
Keywords/Search Tags:Gigabit Ethernet, Logic Design, FPGA, UDP/IP, Nios Ⅱ
PDF Full Text Request
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