The Optimization And Implementation Of HEVC Real-time Decoder Based On DSP

With the rapid development of digital video application industrial chain,the existing video compression technology can't satisfy people's growing demand for experience.Users would like to see the video of high definition,high frame rate and high compression ratio.According to the needs of users,this thesis puts forward the following research objective:based on HEVC standard,achieving 1080P video DSP real-time decoder which can be decoded with the speed greater than 25 FPS.In order to achieve the research objective,this thesis will mainly focus on the following four parts.The first part is the study of the decoding principle.This thesis studies the HEVC hybrid coding framework and the key technologies.This providing a theoretical basis for decoding system optimization and implementation.The second part is the optimization of video decoder.On the basis of theoretical research,this part will talk about HEVC decoder implementation including the C language optimization and DSP optimization:C language optimization consists of structure,memory and performance,and DSP optimization consists of the application of instruction set,Software Pipeline Loop and Cache.The completion of the optimization work greatly improves the time performance of each decoder module,which also laid a good foundation on verifying the decoding system.The third part is the adaptation of video transmission.This thesis proposes a transmission adaptation scheme based on RS channel coding according to the Network Abstract Layer in HEVC standard:employing the redundancy packages repeating transmission to protect important video information,and the RS channel coding with highly error correction ability to restore the errors and lost information from the channel transmission.This thesis expounds the RS decoding principle and the implementation process,and applies the C language and DSP optimization on mononuclear DSP to realize over 10M bit rate,25 FPS real-time decoding performance.The fourth part is the implementation of the multi-core system.On the basis of optimization work on the HEVC decoder and the RS decoder,this thesis studies the implementation methods of the HEVC parallel processing technology.The multi-core system structure designing from balancing load,reducing data throughput and delay,and this thesis also expounds the working principle of the system and IPC(Inter Processor Communication).The system makes the most use of the processing performance of multi-core processors,the test 1080P video decoding speed could be 25 FPS or more,which is the objective of the thesis.To achieve the goal of this study is of highly practical value and research significance.On the one hand,it provides possibility of real-time decoding on DSP platform,which will bring broad application prospects in the field of high-definition video.On the other hand,the optimization scheme and multi-core parallel processing structure this thesis puts forward will bring great reference value and research significance for other platform's realization and implementation of real-time encoder.