Design And Implementation Of Logic Built-in Self-test Compatible With A Power Architecture Microprocessor

Integrated circuit testing is a critical step in ensuring chip quality,a negligible mistake can cause an enormous loss,so IC testing has always been a key issue in the field of IC research.The scale and complexity of ICs are greatly enhanced by the advent of ultra-large scale integrated circuits and system-on-chip.The traditional scanning path method is difficult to achieve in some circuit tests because of the high cost of test and the excessive demand of test vector storage space.The built-in self-test(LBIST)embeds the test system into the chip,not only simplified the test procedure,reduced the cost of testing,shorten the test time,but also have an advantage of enabling field testing and speed testing.Based on the company project,the LBIST was embedded in the core digital logic module of a Power architecture microprocessor chip,aiming to make it meet the DFT design rules and achieve fault coverage requirements(96%).The core module of the microprocessor was used as the test object.The LBIST preprocessing is carried out at first.Then,according to its internal structure and considering the hardware area and test time,32 scanning chains were inserted,the maxmum length scan chain is 1002,and the total number of fault points is 3553661.On this basis,the basic structure of logic self-test was introduced in detail,and the three functional modules of logic self-test: test vector generation module,test control module and response compression module were designed and implemented.Besides,a series of methods were adopted to to improve the LBIST test efficiency and improve the test fault coverage,such as inserted phase shifter,weighted pseudo-random,secondary capture,inserted test points and so on.In addition,a test verification platform was set up for fault simulation and simulation test process.In order to improve the fault coverage of LBIST,the test vector generation module has been optimized.First,the linear feedback shift register was chosen as the basic structure of the test vector generation module.According to the internal logic of the microprocessor,the phase shifter was added to reduce the correlation between the test vectors and increase the randomness.The test efficiency of each scan chain is weak,so the weighted set is generated by the insertion weighter to test the difficult point of the test to improve the test efficiency of the test vector.In addition,double-capture techniques were used in the test capture phase.The verification results show that the designed LBIST can be optimized with the correct signature.The tested microprocessor module increases the original fault coverage from 93.19% to 96.47% when the test vector is 40000.In order to further improved the test fault coverage,some observe points and control points were inserted to enhance the observability and controllability of the circuit,the coverage rate increased to 97.48%.Finally,based on the LBIST combined SCAN test technology,the fault coverage was further increased to 99% or more.