Analysis Of Bit Error Rate Caused By Power Noise In High-speed Link

Currently,with the rapid development of the electronics industry,the data rate is increasing rapidly.In the past,when designers faced low data rates,they made simple connections to the device,so that can make the system work properly.But now,this way is no longer feasible because of the high data rate.Designers often encountered some new problems that are mostly about signal integrity issues.With the continuous improvement of the data rate,and the complexity of system design,it is very important to predict the performance of the system accurately.Usually,the tool used to measure a system performance is eye diagrams.Eye diagram is divided into the traditional eye and bit error rate eye diagram.Traditional eye diagram is prone to over-design of the system.Therefore,the error rate eye diagrams is more valuable for the design.The signal is affected by a series of noise during transmission,which include crosstalk,inter-symbol interference,and power noise.These noises distort the signal waveform,which is shown in the eye diagram as a decrease in eye height and eye width.Therefore,the eye diagram has an important role in engineering design.The study of crosstalk and inter-symbol interference is relatively mature,but the power noise in the system also accounts for a large proportion of total noise.And it directly affects the error rate of the system,which makes the power noise can not be ignored.Therefore,a method is urgently needed to calculate the effect of the power supply noise on the eye diagram.Due to the importance of bit error rate and the power supply noise mentioned above,this thesis presents a way to solve the error rate of the signal in the system based on DDR4 memory structure.DDR4 bus is a parallel structure.And in all parallel structures,DDR4 has the highest transmission data.Therefore,some problems about signal integrity can be better discovered.For this thesis,DDR4 is represented in the crosstalk,inter-symbol interference and power supply noise and other issues.In this thesis,first of all,HSPICE is used to simulate the designed system.And then MATLAB is used to deal with these data.For the above two kinds of noise,we take different ways to solve the probability under different sampling time and sampling voltage and then combine the two results.Thus the error rate is obtained.Finally,these above will be drawn into a bit error rate eye diagram.The bit error rate eye diagram can evaluate system quality from the perspective of statistical domain,which will provide more reference for designers and then improve the design of the system.For the above method,this thesis developed it into a tool based on MATLAB.The software can provide designers with a convenient way to calculate the eye diagram which can provide more help to the design.