Optimized Design Of Low Phase Noise For LC VCO In CMOS Process

A precise signal being extracted from a very noisy environment is the most valuable property of the PLL.This property is widely used in communication field,such as local oscillator signal locking in radio frequency transceiver.An essential part of PLL is voltage controlled oscillator,whose phase noise performance determines the performance of receiver.The design of low phase noise VCO has become a difficulty,due to some factors such as the low quality factor of on-chip inductors,transistors flicker noise and power supply noise.In this paper,the design of S-Band CMOS inductor and capacitor voltage controlled oscillator achieves a better phase noise performance,which can provide a good signal to the wireless communication system.Firstly,this paper introduces the current development situation and principle of oscillator,then it expounds the importance of performance parameters and mathematical model of VCO,also comparatively analyzes the circuit structure of LC VCO and ring oscillator,finally it combines with the application requirements of PLL selected LC VCO structure.The whole circuit design is divided into two aspects: first,a new type of switch capacitor array is designed to reduce the self-noise of LC VCO and expand the tuning range,which realizes digital tuning;noise filtering technology is used to reduce outside noise interference;the optimization of integrated inductor improves the quality factor of resonant network.Second,to reduce noise of the linear regulator for power module,the LDO of voltage regulator module structure is designed,the bandgap reference circuit is simplified,and the two error amplifiers share a power mirror circuit to reduce the noise.In the aspect of layout design,the LC VCO layout is planned from the perspective of reducing parasitic resistance capacitance and meeting the symmetry of resonant network;the LDO layout is designed from the perspective of overall layout and reducing the noise,which matches the PLL overall layout.Then post-layout simulation is performed for LC VCO and LDO of power supply module,both of the simulation results meet the design requirements.The PCB test board is designed during taped out,and the test on the PLL chip is completed,in the meanwhile.The paper also focuses on verifying the influence of the different noise LDO to LC VCO phase noises,the test results meet the design requirements.Based on 0.35μm CMOS process,the low phase noise LC VCO which is applied to PLL is designed in this paper,and taped out for verification.The result of test indicates that the tuning voltage varies from 1.95 GHz to 2.4 GHz as the power supply voltage is 3.3v.When the LC VCO working at 2GHz,the excellent phase noise performances are-110.8dBc/Hz at a 100 kHz offset,-132.8dBc/Hz at a 1MHz offset,and power consumption is 34 mw.The above indexes meet the using demand of the PLL.