The Design And Implementation Of A Hardware Platform Based On Domestic Components For MIMO-SCFDE Systems

Telecommunication systems based on the technology of multiple input multiple output (MIMO) and single carrier frequency domain equalization (SCFDE) get more widely used in wireless wide band communication. This thesis presents the design of a general-purposed hardware platform for MIMO-SCFDE systems. The platform should be able to flexibly implement the physical layer algorithms of a modem in different telecommunication systems, so as to act as a demo to prove the correctness of the algorithms.The platform is designed following the principles of flexibility, high performance and low cost. The three principles being mutual excluded, a balance must be found among them during the design. The platform includes the central processing module based on FPGA, the transceiver link module based on DAC and ADC, the clock system module based on clock generator, the power system module and the overall controlling module based on ARM. Being the key point of the platform, the central processing module makes use of the multi-boot function of some FPGAs to implement the design of "area of circuits in FPGA reduced at the cost of the storage in Flash" for multi-mode systems, which is an innovation in the design and strikes a balance among the three principles. This idea could also be found in other parts of the platform.In the design, domestic components are to be used instead of imported ones whenever possible. As for the relatively fewer choices and lower performance of domestic components, it’s a difficulty as well as an innovation of the platform. In order to maintain the basic flexibility and high performance of the platform, it’s designed all using domestic components except for FPGA, DA/AD, and clock generator.The MIMO-SCFDE hardware platform is implemented based on the design and takes comprehensive circuit tests. Finally the platform acts as a hardware platform for an actual telecommunication system, and passes the lab and the field tests, which proves the correctness of the design and the robustness of the platform. The domestic alternatives for FPGA and ADC are also provided in the thesis for the further evolution of the platform.