The Verification Of Power Sensor Signal Processing Module Based On UVM Methodology

With the development of semiconductor technology,the integration is getting higher and higher,the capability of integrated circuit design is also rising rapidly,so the scale of the integrated circuit is more powerful and complex.As the result,The complexity of its verification has increased,and the traditional verification method is difficult to meet the current situation.This article describes the UVM(Universal Verification Methodology)to solve this problem,which inherits the advantages of VMM and OVM。Now it has become the most popular and most advanced standardized method of verification.The UVM is an object-oriented programming methodology which uses the System Verilog language,while ensuring compatibility with the hardware description language.The main work of this paper is to analysis the function of the Power Sensor Signal Processing Module and build the UVM verification platform for it.The module which required to verify includes its sensor serial signal identification in therm or voltage mode,the interaction with PCB bus,the forced or not forced generation of temperature or voltage warning signal,writing the sensor configuration information,Time Detection sensor configuration information,Time Detection sensor data output,timestam,scan chain and initialization.These modes are configured by 32-bit address lines,64-bit data lines,1-bit read and write flags with their parity bits.At the same time,there are acknowledge and valid bits for request and reply,and port reset bits to control the bus interaction is correct.As the combination of the above signals is very complex with a number of interesting verification boundaries,this thesis developed a corresponding verification plan firstly,including functional coverage model,assertion coverage model,transaction level constraint generation and then apply many built-in UVM mechanism to ensure that the following simulation is comprehensive and correct.For the functional verification requirements and platform reuse,the UVM verification platform is built with the variety of UVM built-in mechanism,such as virtual sequence mechanism,register model,factory mechanism,callback mechanism,config_db mechanism.The UVM is essentially an extension library for its verification language System Verilog,so it also continues to use a variety of unique components such as virtual interface,assertion,covergroup,and constrained randomization.After completing the UVM verification platform,you can get the simulation information file and coverage report by NCSIM and use v Manager to analyze them.According to the comparison between the results of assertion,function coverage,error-free simulation information and the technical documents,it is proved that the UVM has the advantages of flexibility,reusability and shortening the verification period without losing the correctness and comprehensiveness of verification while assertion and function coverage converge to 100%.