Research And Design Of Digital Controlled Oscillator And All-Digital Phase-Locked Loop Oriented Synthesis

With the rapid development of digital integrated circuit technology,the signal voltage margin on the chip is getting smaller.Because the noise from digital circuits of SOC,the traditional charge pump PLL is more difficult to adapt the requirement of modern wireless communication.In addition,in a deep-submicron CMOS process,time-domain resolution of a digital signal edge transition is superior to voltage resolution of an analog signal.Under this background,flexible and low-cost all digital phase-locked loop(ADPLL)become a research hotspot.It is not sensitive to the noise of digital circuitsThe traditional ADPLL build digital controlled oscillator(DCO),which generally is analog designed.So there are many restrictions on the entire ADPLL design cycle and process migration.In this paper,a new type of integrated digital oscillator is proposed.By introducing the synthesized DCO,the ADPLL in this paper all functional blocks can be synthesized.The entire circuit can enjoy all the advantages that is brought by the progress of digital process size,improve the portability,and promote the application of ADPLL in IC industry.For the oscillator,this paper presents a comprehensive three-level ring vibration DCO architecture and the frequency resolution is determined by the minimum a available transistor size.The diode-connected load reduces the effective drain-source voltage for the tri-state inverter cell and enhances the frequency resolution by reducing the on/off current difference.As a result of the introduction of the synthesized DCO,ADPLL digital control signal significantly reduced.So this paper designs an digital loop filter,which divides the traditional loop filter into two-stage structure,and makes the integer and fractional parts of the digital control signal have different filtering characteristics and loop bandwidth.Improve the loop lock time and the stability of the output frequency.This paper also designed a loop fast lock frequency detection controller.It detects circuit output signal to quickly capture the target frequency,and can adjust the DCO tuning mode,while compensating the phase difference to patch mode switching error.The introduction of frequency detection controller greatly improves the loop lock time.Simulation shows an increase of more than 65%.Based on the 0.18μm CMOS process,this paper designs an ADPLL with the synthesized DCO for the 2.4GHz-band.Simulation under the 1.8V supply voltage shows that the ADPLL lock time is less than 1μs at 2.4GHz,output frequency achieves from 2.2GHz to 2.7GHz.The period jitter is less than 10ps@2.4GHz.