Research And Design Of Low Voltage And Low Noise CMOS Amplifiers

The low noise performance of integrated circuits is very important in engineering designation. Low noise amplifier is used in the frond-end of the acceptor of in radio frequency communicating systems should own the characters of high gain, low noise, less consumption and wide band. Low noise operational amplifier is the basic of the integrated circuits. The properties of high gain, low noise, great CMRR, enough phase margin, low power consumption must be achieved. In order to improve the properties of communicating system and the integrated circuits, this thesis researches and designs the low noise CMOS amplifiers. The main researches in this thesis are including:Firstly, this thesis based on the theory analysis of bandgap bias reference without resistor, utilizing the feedforward compensation of current, a source of low noise bandgap reference bias voltage is designed and simulated in SMIC 0.18μm CMOS process. Results of simulation shown that the output voltage of the designed BGR are about 1.1V, the variation of reference voltage was only 400μV, achieved the temperature coefficient (TC) of 5.8ppm/℃. The output noise voltage is 3.1n V/√Hz at the point of 1Hz, and 0.003nV/√Hz at the point of 1 KHz, owned the superior noise character.Secondly, with utilizing the noise cancelling and gm-boost techniques, a narrow-band LNA adopted the common-gate noise cancelling circuit, and a wide-band embodies common-gate series in connection with a common source by a resistor as feedback to be the second noise cancelling stage. The narrow-band low noise amplifier (LNA) and the wide-band LNA designed and simulated in Radio Frequency CMOS process. Simulation achieved the narrow-band gap wide of 600MHz. the gain was 18dB-19dB, the noise figure was 2dB-2.3dB. The wide-band LNA noise figure was 1.6dB-1.9dB. When frequency changes from 2GHz to 3.5GHz, the variation of gain was from 20.5dB to 21.2dB. The ldB point was -15.6dBm.Finally, this thesis analyzes the DTMOS noise characteristics, analyzed and designed a three stage low noise operational amplifier which employed the cross coupling input stage of current mirror load, the miller and AC-boosting complementary techniques, then improved the operational amplifier with DTMOS. This work simulated and designed in SMIC 0.18μm CMOS process. Results shown, phase margin was 60.9° first stage gain was 54dB, second was 104dB and the whole gain was about 132dB, CMRR was less than -100dB in band wide of 13.75MHz. The noise was 58.3nV/√Hz at the point of 1Hz,0.28nV/√Hz at the point of 1 KHz. After improving, the simulation achieved the noise of 35.3nV/√Hz at the point of 1Hz and 0.24nV/√Hz at the point of 1 KHz. in the end the noise of DTMOS operational amplifier owns better noise property.