| The development of technology size and bit density has increased the storage capacity and lowered the price for NAND flash memory,which promoted the adoption of flash memory in storage system.However,the weakness of these developments is the degradation of reliability,which raises the raw bit error rate(RBER)of data.Therefore,the error correction capability of error correction codes has to be raised as well,to guarantee the reliability of data.Equipped with strong error correction capability,low-density parity-check code(LDPC)has been widely used in state-of-the-art NAND flash memory.Meanwhile,long read latency is required to gain the probability information for LDPC decoding,when the data to be read has high RBER.This work focuses on the degraded performance issue caused by bad reliability.We make the following three main contributions in this work.Firstly,we propose an access latency model.By analyzing the relationship between the REBR of data and access latency,we propose a read and write access model based on the reliability of flash data.The model shows that there exists tradeoff between read latency and write latency.When a data page is written with long latency,it has low RBER and can be read with short latency.On the contrary,if the data page is written with short latency,it has to be read with long read latency due to the high RBER.This model presents theoretical basis for the next two approaches for performance improvement.Secondly,we propose an access performance improvement approach based on flash access characteristics.We define three types of data: read-only,write-only and interleaved-access.Based on the analysis for the read and write access of several workloads,we made the observation that most read requests access read-only data pages,and most write requests access write-only data pages,while only a small part of read and write requests access interleaved-access data pages.Recall the access latency model,this work first proposes an access performance improvement approach based on flash access characteristics.This work first presents an access characteristics identification approach.Then considering the identified access characteristics,we regulate the access latency of data pages for performance improvement.Finally,we propose to improve flash read performance based on the error characteristics of NAND flash memory.Since the read performance will be degraded when the data to be read has high RBER,there are many previous works focusing on the reduction of RBER for read performance improvement.However,they did not take the error characteristics of flash memory into consideration.In this part,we first studied the mechanism of error occurrence and various error sources.Then we present the error characteristics,including inter-state asymmetric and intra-state asymmetric.Bearing these two types of asymmetry in mind,we propose to exploit them for read performance improvement.In each part,we conduct experiment on simulator to verify the effectiveness of the proposed approaches.Experiment results show that our methods can significantly improve flash access performance with small overhead. |
