Reading Circuit For RFID Tags Based On Amorphous Oxide Thin-film Transistor

The amorphous oxide TFTs represented by a-IGZO TFTs has the advantages of high field-effect mobility,good uniformity over large area and low process temperature,has been extensively studied in radio frequency identification tags.Simultaneously,the projected cost of a-IGZO TFTs is low,which is of practical significance to expand the application of radio frequency identification tags.Due to the lack of complementary devices,the power of the tags for the composite radio frequency identification protocol is too large to limit the tags recognition distance and data storage capacity.A low power asynchronous reset D flip-flop circuit is designed.The circuit using dynamic load to reduce the static power consumption by reducing the probability of conduction.The dynamic load D flip-flop retain the advantages of NOR gate delay while effectively reducing static power consumption,easing unipolar circuit design in the gate delay and power consumption.The existing ring oscillator scheme is discussed and the feedback Pseudo-D ring oscillator circuit is proposed.Adding positive feedback to the Pseudo-D scheme to improve the pull-up speed of inverter,thereby increasing the oscillation frequency.At the same time,still maintain the Pseudo-D scheme low-power performance and achieve full output swing at low supply voltage,suitable as a clock generation circuit.Finally,a tag storage read circuit is designed,consists of Johnson counter and monotype complementary gates.By utilizing the complementary signals to drive decoder based on monotype complementary gates,propagation delay can be declined,and redundant current can be reduced.The Johnson counter reduces the number of registers.The new circuit can effectively avoid the glitch generation,reduce circuit power consumption and delay,and finally output a stable high peak-to-peak pulse.The simulation result demonstrates that,the dynamic load D flip-flop reduces the power by 24% ~ 40% in different cases compared with the non-optimized D flip-flop.The same 100 KHz clock drive signal is generated,the feedback Pseudo-D scheme reduces the power by 82.3% compared to the Pseudo-E scheme,and the output value is higher.The same clock signal to drive 8 × 8-bit ROM,the power of the Johnson scheme is 40.3% lower than the ring shift scheme.After using the dynamic load D flip-flop to optimize the Johnson scheme,the power of the read circuit is reduced by 26.50%.