Research On FPGA-based Image Detection And Matching Algorithm For FAST Feature Point

Image feature detection and matching technology are fundamental operation in visual processing.They are widely used in image fusion,image correction,objection recognition and tracking,etc.SIFT(Scale Invariant Feature Transform)and SURF(Speed-up Robust Feature)are mature image feature detection and description algorithms.But those algorithms have a high degree of computation complexity and need to construct scale space.They cannot process real-time image and are not suitable for portable terminals to implement.In this thesis,a image feature detection and matching system is designed which is based on the SOC(System on Chip).The FAST(Feature from Accelerated Segment Test)algorithm is used to implement image feature detection,the BRIEF(Binary Robust Independent Elementary Feature)algoritm is used to implement image feature description and haming distance is used to describe the difference between different BRIEF descriptor.In this thesis,the whole system is designed using Xilinx Zynq-7000 SOC.The system hardware and software functions are divided properly,so that they can cooperate with each other.The FAST feature detection,BRIEF feature description,and matching part are implemented using logic circuit of SOC to accelerate these algorithms.Data scheduling is implemented in processing system of SOC to achieve the data exchanges between logic circuit and external memory through DMA(Direct Memory Access).The logic circuit is controlled through data bus.The central part is hardware circuit of visual processing algorithm.After the circuit is designed,the functional verification is completed,and comparing with software algorithms is necessary.The detection-description coprocessor is the combination between FAST feature detection circuit and BRIEF feature description circuit.Its input and ouput interfaces are based on AXI4-Stream protocol.The coprocessor and external memory are connected via DMA and data bus to solve the bottleneck of data transmission.The feature matching circuit is used as matching coprocessor which has the same architecture with detection-description coprocessor.The functions of the two coprocessors are verified under the SOC platform.The coprocessors are controlled through processing system of SOC.The two coprocessor circuits can operate at clock frequency up to 100 MHz.Detection-description coprocessor circuit can process 290 frames per second for 640×480,8 bit grayscale image.The design satisfies the requirement of real-time image processing.