Performance Of Polar Coded Systems And CA-SCL-Based Decoder FPGA Implementations

With the development of the society,mobile communication technology has entered the new era of 5G.Polar Code is a popular alternative coding scheme of 5G,which is attracting more and more attention.In recent years,there exists some mature coding schemes like Turbo codes and LDPC codes,these codes are efficient and practical,but their bit error performance has some gap with the Shannon limit.Polar Code is the only coding scheme that can reach the Shannon limit in theory.At present,Polar Code as a control channel coding scheme,has been written in the 5G standard.Polar Code were discovered and proposed by Arikan in 2008 and which is based on the polarization phenomenon of binary discrete memoryless channels(B-DMC).Its coding and decoding are highly efficient and easy to implement,and thus have a wide large application potential.In this paper,we mainly focus on the code-construction methods and decoding algorithms of Polar code under finite code length,and the hardware structure as well as FPGA implementation of decoder based on CA-SCL algorithm.The main work are:Firstly,we first introduce two existing coding schemes-turbo codes and LDPC codes,and their coding and decoding algorithms are introduced in detail.The simulation results show that the turbo code will appear error floor,and for the irregular LDPC,the coding complexity is high.Finally Polar Code are introduced.Comparing the three coding schemes in the three aspects of codeword construction,coding and decoding,the superiority of Polar Code are proved.Secondly,the generation principle of Polar Code is discussed in detail.The variation of parameters in BEC and other channel models during the process of channel decomposition and channel merging are studied.The essence of polarization theorem is analyzed empirically and derived polarization coding theory.According to this theory,the generation matrix and the specific coding flow are studied.Based on the encoding principle,we analyzed several code-construction methods and proposed methods to select information bits and simulated their performances under different circumstances.Simulation results show that Gaussian Approximation has better practical value.Finally,the similarities and differences between the RM code and Polar Code of the Plotkin structure are studied.Then we analyzes the decoding algorithms of Polar Code.On the basis of fundamental algorithm SC,an operation-enhanced LLR-calculation-algorithm and performance-enhanced algorithm,which we called List-SC,are proposed.By allowing more surviving paths in SC algorithm,the performance-enhanced algorithm is close to the performance of ML decoding.CA-SCL is an improved version of SCL algorithm,which is aided by redundancy check codes.During the decoding procedure,it uses CRC code to filter output sequences.Once the checksum is zero,decoder directly produce decoding result and stop iteration decoding.CRC code further improve the error correction capability of SCL algorithm.We use this as the final decoding algorithm in hardware implementation.Finally,we design a CA-SCL decoder based on FPGA.For each part of CA-SCL decoding,the relevant sub-function modules are designed,the verilog design input is completed on Quartus II software,functional simulation and debugging are completed on Modelsim.After the successful simulation,we finally get correct output in top-level module of the decoder.The designed cyclic redundancy SCL decoder achieves the throughput of 6.5Mbps at the operating frequency of 300 Mhz.