Research And Implementation Of Reconfigurable Co-processor Transaction Level Architectural Performance Analysis

Coarse grained reconfigurable architecture has become an important solution for high performance reconfigurable SoC coprocessor because of its high configuration speed,fast calculation speed,good adaptability and low power consumption.However,the traditional performance analysis method of register transfer level modeling is still widely used.To overcome the shortage of traditional performance analysis in flexibility and efficiency,we propose a new method for reconfigurable SoC performance analysis based on transaction data flow graph.This method combined application data flow graph with architectural characteristics through constructing the transaction dataflow graph of reconfigurable coprocessor and labeling hardware performance parameters corresponding to functional properties.The result of the experiment indicates that the proposed method calculate the structure of the reconfigurable SoC accurately and effectively,and benefits the design of architecture and design space exploration.The main work and achievements of this paper include the following four aspects.1.This paper proposed transaction data flow graph,which reflects the characteristics of application and architecture of reconfigurable coprocessor.Through mapping the functional and performance characteristics of hardware modules to application dataflow graph,transaction dataflow graph connected application dataflow,function of hardware and performance,which prepared for building performance analysis model.2.Proposed a reconfigurable coprocessor performance analysis model based on transaction dataflow.After dividing and merging nodes according to the computing mode of reconfigurable architecture,including serial computing,loop computing,pipeline computing and parallel computing,we can obtain the performance model of reconfigurable coprocessor which consists with application dataflow and the architecture of reconfigurable coprocessor.The performance analysis model can effectively guarantee the accuracy of performance analysis3.On the basis of building performance analysis model,a hierarchical performance analysis and search algorithm is implemented.The algorithm uses the breadth first search method to search and count the performance based on the cyclic basic block,branch feature of transaction dataflow and hierarchical performance analysis.Experimental results show that the proposed algorithm can efficiently search the computing performance of the application on reconfigurable coprocessor.4.Completed the software prototype of the performance analysis model,and the RTL level modeling and simulation of reconfigurable coprocessor.The performance analysis of FFT,matrix multiplication and first order smoothing filter is performed on the RTL model.Based on the simulation results of the RTL level model and the performance analysis results of the performance analysis method,we verified the validity and accuracy of the proposed performance analysis model and the efficiency of the performance search algorithm.