The Design Of Low-power Multiplier Based On Dual-logic

Multiplier is the most important component of the CPU and DSP,its power consumption occupies significant ratio in the whole circuit.Hence,the low power deign is important for multipliers.Multiplier is usually composed of a large adder array,which consumes a large amount of hardware resources.Due to the length of the instructions and the size of the data are different in the chips,if we use the 18 Bits multiplier to deal with the data of the 4 bits,it will result in energy consumption and waste of hardware resources.Therefore,the design of configurable multiplier has aroused wide interest of researchers.In this thesis,we study the configurable multiplier as the research object,and the low power consumption as the research object.Based on the traditional array multiplier,using RM(Reed-Muller)low power three input AND/XOR gate logic to build a new multiplier unit module,implement a new multiplier,make it configurable.A reconfigurable low power multiplier which is based Signal blocking is designed.We use signal gating technology to divide the configuration multiplier,build the voltage island according to the different working modes,and use the power gating to provide the power supply voltage,implemented a configurable multiplier with low consumption.According to the contents of this project,this paper can be divided into following aspects:1.Research and analyze the advantages and disadvantages of different structures multipliers.Compare the difficulty level to realizes the various types of multipliers,and introduction their applications.We established the multiplier structure used in this paper is using Baugh-Wolley algorithm,traditional full adder,array multiplier structure,which has the characteristics of wide application,simple structure and easy realization.2.Use RM low power three input AND/XOR gate to build a new multiplier unit module based on dual-logic.Implement a new 18×18 multiplier with the new unit,which has the advantage of low power consumption compared with traditional multipliers.3.Propose the design of configurable low-power multiplier based on signalblocking.Use signal gating technology to divide the configuration multiplier,build the voltage island according to the different working modes,and use the power gating to provide the power supply voltage,implemented a configurable multiplier with low consumption,which support both unsigned and signed multiplication range4×4 to 18×18.Made two kinds of block designs,including fine granularity and partial blocking4.Introduce the principle of several traditional configurable multiplier,compare the advantages and disadvantages of different configurable multipliers.Analysis the internal multiplier signal flow direction,to explore the power consumption caused by the increase of signal flow.In this thesis,using Cadence IC5141 design platform,under the TSMC 65 nm CMOS process,the different multiplier circuits’ schematics and layouts designed,the simulation results show that the power consumption and delay are optimized while the multiplier circuit is configured for low-bits multiplication.