Design、Modeling And Application In True-time Delay Of Silicon-based On-chip Spiral Inductors

With the increasing development of integrated circuit technology and the rapid growth of mobile communication market,radio frequency integrated circuit based on CMOS process has been widely used.Planar spiral inductor is almost needed in all of the important subelement of the radio frequency integrated circuit.Since the inductor performance directly affects the performance of the unit circuit and even the whole system,it is of great significance to improve the quality factor and build an accurate physically-based model at high frequency of on-chip spiral inductor.Firstly,this thesis introduce the basic characteristics of on-chip spiral inductor and the multiple loss mechanism and high frequency effect of planar spiral inductor are analyzed in detail.Then,the influence of the geometric parameters of the planar spiral inductor on its performance is mainly studied and the design flow and optimization rules of on-chip spiral inductor are summarized.Based on these studies,a simplified double-π equivalent circuit model of on-chip spiral inductor is proposed from the point of physical effect of planar spiral inductor,which can effectively explain the effect of planar spiral inductor of skin effect,proximity effect,feed-through capacitance,substrate coupling effect and so on.The parameters calculated from this model can be used as the reference for fitting the data in practice,thus improving the efficiency and accuracy of the fitting.According to the simulation results,the double-π equivalent circuit model after fitting shows excellent agreement with the electromagnetic field simulation results of ADS Momentum over a frequency range from 0 to 15GHz.A six-stage true time delay operating over 2GHz to 12GHz has been designed with planar spiral inductor model proposed in this thesis based on TSMC 0.18μm CMOS process.The entire circuit layout design is completed using Cadence Virtuoso layout-editor and the main performance indexes of true time delay are simulated based on Spectre simulator.The simulated results are given below:in the operating frequency bandwidth,the maximum relative delay is 66ps with less than 11%delay variation and the input and output return loss is better than-10dB.The insertion loss is-23±1.5dB at 10GHz and the worst-case IIP3 at 6GHz is 1.28dBm.The proposed TTD core occupies 1800μmx990μm,respectively.A three-stage true time delay with the same architecture operating over 3GHz to 10GHz has been designed for the limitation of layout area.The chip has been taped out and measured and the results are given below:in the operating frequency bandwidth,the maximum relative delay is 22ps with less than 12%delay variation.The input return loss is better than-10dB and the output return loss is better than-8dB.The insertion loss is-21±2dB at 10GHz.The proposed TTD core occupies 925μmx770μm,respectively.