A Low Power DSP Chip Of PLL Design And Physical Implementation

Since the beginning of 21st century,integrated circuits have entered a stage of rapid development,the complexity of the system presents a rising trend,and the low power consumption of the circuit has become one of the important indexes in the development of integrated circuit chip design.The level of power consumption directly affects the temperature of the chip,thus affecting the packaging cost of the chip design,but also determines the reliability of the chip.The design is mainly for a DSP(Digital Signal Processor)chip low power consumption research,the purpose is to ensure the best performance in the case,to achieve the low power requirements.In order to realize the design requirement of the power consumption of the chip,the phase-locked loop and the back-end physical design of the clock system are studied.First presented the research background and current situation of low power consumption,and then described the design process and design points.Secondly,analyzes the source of the power consumption of the CMOS integrated circuit and the method of reducing the power consumption,including dynamic power consumption,static power consumption.At the same time,introduce the strategies of power analysis at different design levels.Then,the specific circuit design of the PLL is described,and the power consumption of the PLL is effectively reduced by the common circuit multiplexing technology,the reasonable reduction of the circuit current and the optimization of the reference generating circuit.The design of the innovative charge pump effectively avoids the influence of the channel charge injection effect and the clock feedthrough effect,improves the accuracy and stability of the charge pump,thus reducing the noise of the whole circuit.A new clock prescaler is added to the base of the basic charge pump phase-locked loop to achieve more step-by-step and fractional frequency division of the PLL.The ultimate realization of the clock system low power consumption and high precision design requirements.Finally,under the premise of satisfying the requirements of design constraints,the specific design of the layout and routing is introduced in the back-end physical design of the chip.Based on the GSMC180nm process,in the 1.8V power supply voltage,open all peripheral clocks and turn off all I/O,DSP chip running at 150MHz clock frequency conditions,the actual measured chip power consumption of 49.239mw,in line with the project’s low-power design requirements(power consumption is typically 60mw).