Research And Design Of AXI Bus Structure With Built-in Distributed Crosspoint-queued

The coming era of multi-core have extend the pace of ascension for the performance of processor.At the same time,the coming of multi-core have also brought a lot of technological challenges.As the transmission channel of data exchange for inner IP modules,on-chip communication module is one core technology for the design of SoC.How to design a high performance,low cost,low latency,high parallelism and high expandability interconnection structure for the multi-core processor SoC(MP-SoC)which has become a hot research field is priority issues in the process of MP-SoC design.Although the structure of on-chip communication mode which based-on shared bus is flexible and simply to realize,the poor expandability make it seem hardly to meet the growing performance requirement of MP-SoC.The anther on-chip communication mode which based-on crossbar or NoC(Network on chip)has many good features,such as high transmission bandwidth and high expandability and so on,but it’s structure is more complex,and would cost more resources to realize it.The complex design requirements of MP-SoC design make designers begin to attempt a new interconnection communication structure,which adopt two or several different communication structures to compose a whole on-chip communication module.The different communication structure can be used to meet different bandwidth requirement between the different IP modules.This dissertation design a mixed interconnection communication structure which composed by shared bus and crossbar.And use this mixed structure to realize communication of one MP-Soc within integrated with four cores.To realize communication between cores and other IP module,the dissertation adopt the most general on-chip shared bus,AMBA 3.0 AXI bus,which is more mature than other on-chip bus.When need to occupy transmission channel of AXI bus to transmit data,the core shouldemit occupancy request to AXI bus firstly.After acquiring arbitration permission from AXI bus,cores could communicate with slave module through the AXI bus channel.The arbiter can avoid the phenomenon of resource competition between cores.On the other hand,the design of MP-SoC based-on AXI bus usually use shared Cache structure to realize inter-core communication.But the communication efficiency of this inter-core communication structure would become lower as the number of core increases.To satisfy the needs of high-performance communication between four cores,this dissertation adopt Crosspoint-Queued crossbar substitute shared Cache to form a distributed point-to-point interconnection structure.As a new crossbar structure,Crosspoint-Queued structure has better transmission efficiency,and is easier to realize than other crossbar.On the basis of existing research,the dissertation has confirmed the best scheduling algorithm for Crosspoint-Queued structure firstly.And combined with the knowledge of queuing theory,the dissertation build a 4×4 Crosspoint-Queued structure model by MATLAB/Simulink.After simulated the model,the optimal depth of inner queue has been founded.On the basis of the above research,the dissertation has made a RTL design for this mixed on-chip communication.In order to verify the correctness and completeness of the RTL code,the dissertation has made simulation and verification for the code by some EDA tools.The results from simulation and verification indicate that the design of this dissertation,AXI bus with built-in distributed Crosspoint-Queued structure,can achieve every function of on-chip communication completely.At last,this on-chip communication structure has been applied to a quad-core SoC project,and the quad-core SoC has been fabricated successfully.