Research And Design Of Real-time Video Dehaze System Based On FPGA

When a picture is taken in the haze,some information is attenuated during transmission due to being scattered by haze particles in the air.At this time,hazy images have less valid information and thus cannot be applied directly by researchers.Currently,dehazing of hazy images has become an indispensable preprocessing process in many fields of image research.Therefore,image dehazing technique has unique and high practical significance.Based on investigations about current image dehazing technologies and achievements,integrated with learned knowledge and profession skills in the field of microelectronics,relying on hardware and software co-design advantages of SoPC FPGA,the design of SoPC video dehaze system with low-cost,high-stability and high-performance was researched and implemented.The main research contents of this thesis were concerning about the design of SoPC system,the speed of optimization dark channel prior algorithm and the improvement of the haze removal in sky region.The hardware and software co-design was carried out and divided into three parts,including research and implementation of software dehazing algorithms,customized design of SoPC system and software algorithm optimization and hardware acceleration design.(1)Research and implementation of software dehazing algorithms:The histogram equalization algorithm and dark channel prior algorithm were adopted as core algorithms,which adapt to the multi-scenario engineering requirements.Firstly,the algorithm prototypes were developed by utilizing image input and output interface and image processing functions provided by Matlab.Then the design of platform-independent C-Model was implemented with C language on Visual Studio.(2)Customized design of SoPC System:Based on analyses of hardware requirements of dehazing algorithms,the developing scheme was formulated.The Altera Qsys tool was applied to design the SoPC system architecture.On Altera Quartus and Modelsim software platform,the design of VGA controller based on Avalon-MM was implemented by the Verilog hardware description language.Afterwards,the algorithm C-Model was ported to the SoPC system and downloaded to the target FPGA hardware platform for the hardware and software joint debugging.(3)Software algorithm optimization and hardware acceleration design:The algorithmic complexities of box filter and local minimum filter were optimized to O(n)and were irrelevant to the size of filtering window.The designs of hardware accelerators of box filter and local minimum filter were completed by using the Verilog hardware description language.A dehazing scheme combining dark channel prior algorithm with sky recognition algorithm was developed.The final results showed that previous severe problems like color cast and halation in the sky area of dehaze results were solved by the proposed dehazing scheme,the information was restored validly which was hiden by haze and can not be seen by human eye and the running speed of dark channel prior algorithm were improved significantly.The frame image processing time of histogram equalization algorithm was able to reach 26.3 milliseconds and the optimized dark channel prior algorithm was able to reach 3.98 seconds,which met the requirements of engineering project.