| With the development of semiconductor technology,the performances of the processor and the main memory is being improved continuously,but the improvement of the main memory access speed is behind the processor execution speed,causing the speed difference between them is more and more serious.In order to solve this problem,Cache memory is given the responsibility and got considerable development.However,with the continuous optimization of the processor architecture,Cache consistency gradually comes out and the performance of it affects the processor performance.Therefore,solving the cache consistency in computer system is very important to improve the performance of computer system.In this paper,bus snoopy protocol and directory protocol were deeply researched and analyzed,their deficiencies in efficient utilization of bus resources and access delay were improved.In order to improve the effective utilization of bus resources,the D-Cache virtual bus architecture mode was adopted to realize the point-to-point consistent transaction transmission,thus avoiding the idle bus occupied that was caused by the polling query method when adopting the broadcast consistent transaction.Meanwhile,a cache consistent protocol—CCPBVB snoopy protocol,based on write-back strategy,was designed to reduce the access delay caused by the ping-pong phenomenon in cache memory.The protocol determined the write strategy by sharing the data attribute value in the private cache,adopted the write-update strategy and write-obsolete strategy respectively according to the shared data attribute value.It reduced the access delay of the directory protocol without causing the number of the bus consistent transaction increased dramatically,improving the overall performance of the computer system.Experiments were carried out on GEMS multi-core simulator.The SPLASH-2 parallel program test set was selected and the test data was analyzed under different cache consistent protocols.The results showed that the CCPBVB snoopy protocol improved bus utilization and reduced access delay. |