OpenMP Cost Model For Heterogeneous Structures And Loop Interchange Based On Profitability

Heterogeneous processors becomes more and more widely used in the field of high-performance computing.It integrates different types of processor cores on a single chip,providing great potential for parallel computing,but it also presents a huge challenge.People need to master more advanced programming models and richer architectural knowledge to write parallel code that takes full advantage of heterogeneous resources.This is very difficult for ordinary programmers.So the parallelization compilation becomes the main way to quickly get efficient parallel program.At present,the parallelization of the heterogeneous architecture of the compiler technology has made fruitful research results,but there are still many problems need to be analyzed and resolved.This paper explores the OpenMP cost model and the loop interchange problem of the heterogeneous architecture involved in the parallelization process.The main research contents include:(1)In view of the traditional compilation framework,the cost model can not meet the demand of the new architecture and the programming model.The OpenMP parallelization cost model for heterogeneous processor is designed.The cost model is composed of processor model,cache model and parallel model.The parallel cost model is modeled according to the characteristics of the OpenMP parallel programming model.A parallel cost model for heterogeneous architecture can help the compiler identify accelerated loops.Experiments show that the cost model can speed up the program and achieve high performance on the target platform?(2)In order to solve the problem that the parallelization may occur after the loop interchange of nested loops,a loop interchange algorithm based on the advantage is designed.In the begining,this algorithm make loop interchange by the data locality of loop,then evaluating the profit of loop parallel,and strip mine the loop by profit.Finally,implement loop interchange,and searching the largest parallel cycle times.Experiments show that the use of loop interchange algorithm can help the compiler to select the appropriate order of the nested loop and improve the program parallelism.Finally,a cost model is constructed in the GCC compiler,and the algorithm based on the beneficial loop interchange is implemented.The experimental results are carried out on the domestic processor.The test results show the effectiveness of the method.