Multi Thimble Stripping Process Mechanism Analysis And Optimization Of Ultrathin Chip

Ultra-thin chip is inevitable trend in the development of Integrated Circuit(IC)industry,however,ultra-thin chip high density,fragile,easy bending also brings great challenge to the existing packaging technology.Chip Stripping is one of the core technologies of IC encapsulation,and it is great significant to realize the ultrathin chip without loss and high efficiency.Ultra-thin chip shatter easily,and it is difficult to strip.This paper focus on the multi-thimble stripping process,the main research content and the innovations including:(1)Modeling and emulation of the multi-thimble stripping process.In this paper,introduces the working condition of the multi thimble stripping process,and according to the working condition,we have established finite element model and virtual crack closure legal(VCCT)method.(2)Mechanism analysis of multi-thimble stripping process.This paper introduces the competition between interface stripping and chip fragmentation,and analyzes the influence of various parameters.In addition,the limitation of conventional multi-top needle technology is analyzed.And it provides guidance for the design of multi-thimble and device structure design.(3)Put forward and simulate the multi-thimble stripping technology.we detailed design the technological action process consider the new process.Based on this,we have designed a new type of multi-pin stripping device to realize the high efficiency and high reliability of the ultrathin chip.(4)The advantages of multi-thimble stripping technology for ultra-thin chip are verified.By building a multi-thimble processing platform,in this paper,we compared the process of multi-top stitching process with the optimized and multi-thimble,and proved the feasibility of the process.In conclusion,through the simulation research of the ultra-thin chip peeling process,the optimization process and device mechanism of the multi-thimble ultra-thin chip are given,which lays the foundation for the realization of the high efficiency and reliable peeling of the ultra-thin chip.