Design Of Synchronous Rectification Control IC For Hign Efficiency Motor

Under the background of surging waves in the field of artificial intelligence,integrated circuits(ICs),as the smart core of diversified applications,are sought after by a large number of investors.In the work report of the government in 2018,it is more important to put emphasis on promoting the development of industries such as integrated circuits,new energy vehicles and new materials.China’s chip industry started late,and domestic chips have not occupied a place in the tide of economic globalization.Although there have been great advances in packaging and testing,the design aspects,especially high-end chips,are heavily dependent on imports.This requires joint government enterprises to work together for China.Labor-intensive efforts are changing to technology-intensive ones.In terms of motors,motor drive technology is one of the three major technologies for new energy vehicles.Because ordinary motors have low energy efficiency levels and cannot meet new energy emission requirements,high-efficiency motors have emerged.One of the cores of high-efficiency motors is driving ICs.So far,many manufacturers are committed to the development of related motor structures and driving ICs.Based on this,this paper proposes a design method that applies synchronous rectification technology to automotive drive motors.It designs a low-power,low-latency control IC to achieve the high efficiency requirements of the motor drive system.This paper proposes a set of solutions to solve the false triggers that many such chips in the market have in actual measurement,which will lead to the power consumption limited and the chip life limited,etc..The solutions will be studied in the analog circuit part and the digital circuit part,and performance optimization will be done in the following part.This paper designs a high-efficiency motor synchronous rectification control IC.Firstly,it introduces the background technology of high-efficiency motors,and summarizes the research status of this topic at home and abroad.After that,the top-level architecture used in this chip is presented and design indicators are provided.The working principles of each module are described in turn,including the current source,reference voltage source,voltage detection module,UVLO(Under volatage lock out)module,enable module,and driver module in the analog circuit section.Digital circuit part of the minimum on-time control module,the minimum off-time control module,the minimum current control module.Then closely follow the requirements of low power consumption and small delay,simulate the circuit,verify system functions and optimize circuit performance.In this paper,a company’s 0.8μm 40 V BCD(Bipolar cmos dmos)process platform is used to simulate the design of the control chip in Cadence.The switch model is modeled by a company’s test data,and finally achieves the desired goal.