A High-speed High Resolution Pipelined ADC Design Using Positive Feedback Capacitor

Analog to digital converter is the bridge between analog world and digital world.Pipeline ADC is widely used as a common analog to digital converter in the field of communication base station,and its speed and accuracy often limit the performance improvement of the whole system.Due to effects of parasitic capacitance,the feedback coefficient of MDAC in modern high-speed,high-resolution Pipeline ADCs tends to be very low,so that the operational amplifier needs high gain bandwidth product(GBW)to meet establish precision requirements of signal.However,as a bottleneck in high-speed and high-resolution Pipeline ADC,operational amplifier with high GBW often consumes a large chip area,a great power budget and a long designing period which are difficult to accept for modern communication base station systems.Therefore,it is an important way to reduce the overall power consumption of the system by improving the MDAC feedback factor and reducing the MDAC's requirement for operational amplifier GBW.Consider Miller effect,through adding a positive feedback capacitor between input and output of operational amplifier in MDAC,we can eliminate the effects bringed by parasitic capacitance which can lead to decrease of MDAC feedback factor.Thus,the feedback factor will be improved,and the GBW requirement of MDAC and power consumption can be reduced.Based on the SMIC55LLRF 180nm CMOS process,this paper describes the design of a 14-bit 250-MSPS Pipeline ADC with a supply voltage of 1.8V and a signal swing of 1V.The core structure of Pipeline ADC includes sub ADC,MDAC with positive feedback capacitor,two-phase non-overlapping clock generation circuit,digital calibration module and so on.Firstly,this article describes the ADC operating principle,performance index and common structures.Then we analysis the critical circuit design and error sources of Pipeline ADC.Based on the chip area requirement and power consumption consideration,we choose SHA-less Pipeline ADC architecture.In these circuits,MDAC,sub-ADC,bootstrap switch,operational amplifier,and digital calibration algorithm are important modules that affect the speed and accuracy of Pipeline ADC.Later,circuit design and its simulation results of the 14-bit 250-MSPS Pipeline ADC have been fully discussed in chapter 4.Finally,combined with the analysis of the design principles and non-ideal effects of deep-submicron CMOS process,Chapter 5 gives layout design of the 14-bit250-MSPS Pipeline ADC,including the layout of the op-amp and layout of every stage.Through parasitic parameters extraction and post-imitation,we can make conclusion that the Pipeline ADC we design can work normally at a sampling rate of 250MSPS and its dynamic performance is excellent.The ADC achieves 70.12dB signal to noise distortion ratio(SNDR)and 81.02d B spurious free dynamic range(SFDR)at Nyquist input after calibration.Power consumption of the the Pipeline ADC is about 300mW,and chip area is3.144?1.435mm~2,which meet the design requirements.