Research On Key Technologies Of Data Aggregation Under Large-Scale Data Acquisition System

In the fields of geophysical exploration and high energy physics,research on the frontier theories and conjectures of disciplines is often conducted through large-scale physics experiments.Data acquisition system is a very important equipment in large-scale physics experiments.Its core function is to receive the raw data of the front-end acquisition electronics,preprocess the data according to the experimental requirements,and then record it in the storage system,waiting for further analysis.In recent years,with the progress of science and technology,the number of channels and sampling frequency in large-scale sensor arrays are constantly increasing,and the original data rate of data acquisition systems is also increasing.The question that arises is how to improve the data transmission and real-time processing capability of large-scale data acquisition systems.Data aggregation is a very important part of the data acquisition system.It is mainly responsible for timely and efficient organization and aggregation of data,and transmits the aggregated data to the back-end storage system.Data acquisition systems can increase the upper limit of transmission and processing power by improving data aggregation capabilities.Although there are differences in the internal structure of different data acquisition systems,the core functions and workflows are similar,so in theory,a general solution can be used to solve the data aggregation problem of multiple systems.In order to design a high-performance and universal data aggregation scheme,which can be applied to data acquisition systems of various large-scale physics experiments while solving the data aggregation problem of large-scale data acquisition systems,this paper has carried out related research work.Based on the research of reference technology and the analysis of project requirements,following the generalized and standardized design ideas,this paper finally combines software and hardware design to realize a high-speed data aggregation scheme suitable for a variety of large-scale data acquisition systems,which has the advantages of strong flexibility,low cost of modification,stable and reliable data transmission.In the aspect of hardware design,FMC standard is adopted,which can replace the FMC daughter card,change and expand the data interface of front-end electronics connection at low cost,so that the scheme has the ability of adapting to various data acquisition systems from the hardware level.In logic design,a unified specification is formulated,standard interface and data format are used,and different functional modules are divided.It can add custom logic modules conveniently,or modify and replace individual modules according to the requirements,which can meet the various needs of the scheme in practical application.The organizational structure of this paper is arranged as follows:The first chapter introduces the research background and significance of the data aggregation scheme under the large-scale data acquisition system,determines the design objectives of the scheme and the key technical issues that need to be solved,and investigates the current situation and development trend of the typical data acquisition system at home and abroad as design reference,and gives the research content and structure arrangement of this paper.The second chapter firstly clarifies how to implement the key technologies through analysis,comparison and investigation of interface technology,thus establishing the overall design content of the scheme.Then,the overall design scheme of data aggregation is introduced from two aspects of hardware design and logic design.The third chapter introduces the implementation of the front-end data receiving function.Firstly,the FMC daughter card interface type and data rate required by the scheme are analyzed.Then the Aurora IP core is used to receive the high-speed data function,and the blocking mechanism is designed by using the characteristics of the IP core itself which can transmit bidirectionally to ensure that the data will not be lost or retransmitted in the transmission process.The fourth chapter introduces the implementation of multi-node data aggregation.Firstly,this paper introduces the different methods of data aggregation mechanism based on the transmission protocol facing two kinds of data acquisition systems.Then it introduces the interface scheduling mechanism of interface rotation transmission through signal arbitration.Finally,the data cache function based on DDR3 storage function is introduced.The fifth chapter,from the two aspects of logic module design and driver development,fully introduces how the high-speed data transmission function of the back-end data of the data aggregation scheme is realized.Firstly,the basic knowledge related to PCIe bus protocol is introduced as a reference.Then the logic function of calling PCIe IP core and DMA engine is introduced.Finally,the interrupt mode and response mechanism of driver are introduced,as well as the specific DMA transmission workflow.The sixth chapter introduces the results of the logic simulation and the transmission test conducted by the joint workstation.According to the designed test scheme,the function of the logic module is simulated at first,and then the transmission test and blocking mechanism test are carried out on the workstation with PIFC interface card and driver.The test data shows that the data aggregation scheme is feasible.The seventh chapter summarizes the content of the whole paper,introduces the innovation and shortcomings of the work,and further points out the future development direction.