Research And Design Of Steady-state Evoked Visual Stimulator

Brain-computer interface system(BCI)connects the brain or nervous system to the computer to achieve the purpose of direct communication without muscle tissue.The visual stimulator is an important part of the brain-computer interface system based on visual evoked potentials(SSVEP).It induces the electrical activity of the cerebral cortex through blinking at fixed frequencies or periodically changing visual stimuli.The signal is processed to generate the control signal required for communication.The stability of the visual stimulus signal is critical to the normal operation of the brain-computer interface system.In recent years,with the continuous expansion of the application of brain-computer interface systems,there has been a demand for portable,low-cost visual stimulator circuits.In this thesis,firstly,aiming at the shortcomings of the large size of visual stimulator,this thesis proposes the design scheme of using field programmable gate array(FPGA)to realize visual stimulator.The scheme uses ARM and FPGA to realize the design of visual stimulator,and uses the Video Graphics Array(VGA)interface to display graphic stimuli on the Liquid Crystal Display(LCD).The software design part uses Verilog hardware description language to complete the design on Quartus-II15.0 software platform.The design scheme uses ARM to receive the picture information through the serial port,and then transmits it to the SDRAM of the FPGA through the bus for buffering,and then reads the picture to VGA for display.The shape of the visual stimulus signal in the thesis is a blinking rectangular block diagram,and the parameters such as the position,size and color of the block diagram are adjustable.There are two flashing modes of the stimulation module,according to the blackand-white conversion of a certain frequency,or adjusting the gray value of the stimulus pattern to make the brightness of the pattern change,and the value of the gray value is obtained by sine wave sampling,so that the pattern flashing law is sine wave.The picture can be displayed in a rectangular frame to provide reference information for the subject to make a judgment.The picture displayed by the visual stimulator can be configured by itself,so that the visual stimulator can be applied in more experimental paradigms.Finally,the verification experiment of the visual stimulator was carried out,and multiple sets of EEG signals were successfully collected,and the signals were preprocessed to extract the characteristic values of the steady-state evoked potentials.The results show that the FPGA-based visual stimulator designed in this thesis can effectively induce steadystate visual evoked potentials and can meet the requirements of the brain-computer interface.The visual stimulator hardware size:(100×90)mm,meets the design requirements of portability and low cost,and includes dynamic configuration,superimposed graphic display functions,good scalability,richer application scenarios,and good use value.