Algorithm Research And Hardware Implementation For High-speed Quantum Key Distribution Post-processing

Quantum key distribution theoretically guarantees the unconditional security of communication system by combining with the one-time pad encryption scheme,which could construct a secret system that quantum computers cannot break.However,the high processing delay and system complexity of quantum key distribution post-processing have been the bottleneck of high-speed quantum key distribution system,influencing the final secret key generation rate,especially the error correction and privacy amplification.Therefore,for this problem,this paper proposes a one-step post-processing algorithm based on polar codes for quantum key distribution.By analyzing the channel capacity of the legal communicators and eavesdropper in quantum key distribution under the Wyner's wiretap channel model and constructing a codeword structure of polar codes which could satisfy the reliability and security for post-processing,so that the error correction and privacy amplification could be achieved synchronously in every encoding and decoding.Combining the two processing steps into one without additional privacy amplification,it reduces the system complexity and the processing delay of quantum key distribution and could extracts the final key efficiently.Simulation results show that the final key extracted by the proposed algorithm could satisfy the reliability(the bit error rate after error correction?10^-7)and the security(the leaked information?10^-14 bit)in the quantum bit error rate[0,0.08],which could satisfy the requirement of actual quantum key system.In addition,for the key step decoding of polar code in the proposed algorithm,this paper researched and implemented a successive cancellation decoder for quantum key distribution post-processing based on based on the Field-Programmable Gate Array.The decoder adopts the semi-parallel SC decoding architecture and combines the optimization technology of the node interconnect processing element,which implemented a decoder with the codelength 2¹³ bit.The test results show that the maximum error correctable bit rate could achieve 0.427 with the quantum bit error rate 0.08 under the codelength2¹⁰,which satisfy the requirement of proposed algorithm;The maximum frequency of optimized decoder could achieve 138.7 Mhz which increased by 12.9%and the Look-Up-Table of optimized decoder consumed 55114 which decreased by 3.9%under the codelength 2¹³ bit;Compared with the resource consumption of the successive cancellation hardware decoder based on other architectures under the same codelength,the resource consumption of the hardware decoder implemented in this paper is lower,which is beneficial to the long code implementation of the decoder of the polar code.