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Si Anisotropic Corrosion?Preparation And Properties Of ZrCoY And CrNiAu Films Research In Wafer Level Packaging

Posted on:2021-01-09Degree:MasterType:Thesis
Country:ChinaCandidate:P WuFull Text:PDF
GTID:2381330623980562Subject:Condensed matter physics
Abstract/Summary:PDF Full Text Request
The hermetic packaging process is very important in the manufacturing technology of uncooled infrared focal plane array(IRFPA: Infrared focal plane array)detectors.Wafer-level packaging has the advantages of low cost,small size,and high reliability.It is expected to replace the traditional metal package and ceramic package,and is widely concerned in the large-scale production of IRFPA detectors.In the IRFPA wafer-level packaging process,it is usually necessary to make another silicon-based cap(deep etched groove)wafer that is aligned with the detector chip wafer,vaporize the getter in the cap wafer,and then prepare the metal transition layer,Finally,vacuum welding package.Among them,the anisotropic etching process of silicon has the advantages of good uniformity,simple operation and low cost in the preparation of silicon-based caps,and is the preferred method for preparing the cap structure;Zr-based thin film getter has excellent gettering performance,green Environmental protection,low activation temperature,is an important material for the vacuum packaging process of infrared detectors;the metal transition layer uses multi-layer composite material Cr/Ni/Au,which can better meet the welding requirements.In this paper,the anisotropic corrosion mechanism of Si,the getter mechanism of the thin film getter and the design of the welding metal transition layer are analyzed in depth,and on this basis,the corrosion resistance of the Si O2/Cr Au mask layer and the anisotropy of Na OH solution are carried out Corrosion,Zr Co Y and Cr/Ni/Au thin film growth and performance studies have finally achieved wafer level packaging of the IRFPA detector and conducted gas tightness tests.The specific research contents are as follows:(1)The Na(OH)solution was used to etch Si(100)single crystal with Si O2,Cr Au,Si O2/Cr Au as the mask layer respectively.The anti-corrosion effects of dielectric layer(Si O2),metal layer(Cr Au)and dielectric-metal composite mask layer(Si O2/Cr Au)were compared.The Si O2+Cr Au composite mask layer has no cracking and shedding in high-temperature and high-concentration corrosive solution.the mask layer has excellent corrosion resistance.The corrosion surface obtained under the Si O2+Cr Au mask has a small lateral corrosion,and the drilling depth ratio is 0.82:1.Using Si O2+Cr Au as a mask layer,the corrosion rate and corrosion morphology of different etching solution concentrations,different temperatures,and different IPA additions were studied.The study found that the corrosion rate of silicon increases exponentially with increasing temperature.The corrosion rate is the fastest in saturated Na OH solution,and the corrosion rate can reach 15 ?m/min.The corrosion rate increases with temperature following the Arrhenius equation.Increase the activation energy from 0.23 e V to 0.49 e V;the addition of IPA can increase the corrosion rate of silicon.The corrosion rate is the fastest when the amount of IPA is 10 m L in a saturated Na OH solution,the corrosion rate is 17 ?m/min;the corrosion morphology varies with Na OH concentration Increases and tends to be smooth;in low-concentration corrosive solution,the corrosion morphology becomes flat and smooth with the increase of IPA addition.Finally,a silicon-based cap wafer with a flat surface and a clear interface is etched.The cap space area is 18.8×17.8 mm,and the depth exceeds 100 ?m.Using ANSYS software to simulate the stress of deep corrosion,the results show that the maximum stress value corresponding to the corrosion depth of 0.05,0.10,0.15 mm is 51.26,50.74,33.92 MPa,and the corresponding maximum strain value is 0.3744,0.3867,0.2530 mm.(2)Electron beam evaporation was used to prepare the Zr Co Y thin film getter on the Si cap.The effect of the deposition rate on the film surface morphology,microstructure and getter performance was studied.The study showed that: with the deposition rate increasing from 0.5 ?/s To 5 ?/s,the film becomes denser and denser,the roughness is reduced from 3.611 nm to 2.266 nm;after activation at 350 ? for 40 min,the gettering performance of the Zr Co Y film decreases with the increase of the deposition rate,the initial gettering rate is from 33 cm3· s-1·cm-2 decreased to 23.5 cm3·s-1·cm-2.(3)Using DC magnetron sputtering to grow Cr/Ni/Au as the metal transition layer,using ANSYS software to simulate the stress of the metal transition layer,under 1 atm,when the welding width is increased from 100 ?m to 1500 ?m,the maximum equivalent stress is from 186.52 Pa is reduced to 99.882 Pa,the maximum deformation is reduced from 2.7803×10-5 ?m to 1.6853×10-5 ?m;at 3 atm,the maximum equivalent stress is reduced from 559.56 Pa to 298.161 Pa,and the maximum deformation is from 8.3408×10-5 ?m is reduced to 5.0552×10-5 ?m;at 5 atm,the maximum equivalent stress is reduced from 932.6 Pa to 481.23 Pa,and the maximum deformation is reduced from 13.901×10-5 ?m to 8.4255×10-5 ?m.When the welding width is greater than 500 ?m,the maximum equivalent stress and the maximum deformation are basically unchanged with the increase of the welding width.Finally,the width of the metal transition layer is 1500 ?m,and the thickness of Cr/Ni/Au is 100,400 and 150 nm,respectively.(4)Complete the activation of the getter in the vacuum chamber by growing the cap wafer with the getter,and then solder it to the detector chip wafer by solder.The packaged detectors used He mass spectrometer and vacuum thermal conductivity method to test the leak rate and vacuum degree,respectively.The leak rate is 10-4 Pa·cm3/s,which meets the requirements of the US military standard MIL-STD-883;the vacuum degree becomes 1.9 Pa after 15 days,which meets the requirements of IRFPA.The experimental results in this paper have potential application value for wafer-level packaging of uncooled infrared focal plane array detectors.
Keywords/Search Tags:Wafer-level packaging, Silicon, Anisotropic Etching, Getter, Metal transition layer
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