Development Of T-type Three-level Active Power Filter Device Based On FPGA

Active Power Filter(APF),as a kind of harmonic suppression and reactive power compensation equipment,has the advantages of flexible compensation mode,independent of grid impedance and high compensation accuracy.APF with three-level topology has many advantages,such as high voltage withstand level,large compensation capacity,and so on.It has great research and application prospects.At present,the APF digital control system mostly uses Digital Signal Processor(DSP)as its core processor.Its inherent instruction sequence execution mode and interruption mechanism make the system computational efficiency difficult to improve,and affect the real-time compensation characteristics and stability of the system.Parallel execution of algorithm inherent in Field Programmable Gate Array(FPGA)and quasi-analog circuit characteristics can shorten the execution time of control strategy,reduce the delay of control loop,and improve the real-time and stability of the system.In this paper,the design method of APF digital control system is studied and the device is developed based on the core processor of FPGA.The specific work of this paper is as follows:In this paper,the mathematical model of T-type three-level APF in abc static coordinate system and dq synchronous rotating coordinate system is established,and the control strategy of harmonic current frequency division based on harmonic synchronous rotating coordinate system is deduced.According to the cause of neutral-point potential imbalance in three-level converter,a neutral-point potential balance control strategy based on small vector distribution factor is derived.The simulation model is built to verify the above control strategy.In this paper,the characteristics of FPGA and DSP are analyzed and compared.Aiming at the application of FPGA in power electronic converter,the design method,design principle and design flow of Intellectu.al Property Core are studied.According to the general characteristics of power electronic converter control strategy,the design principles and methods of power electronic IP core with guiding significance are put forward.Several reusable power electronic IP cores are designed,and functional simulation and experimental verification are carried out.The prototype of power electronic IP core library is formed.According to the serial-parallel execution relationship of each part of tihe APF control strategy,a complete APF control strategy is constructed in the ’FPGA by building blocks,and its calculation frequency can reach up to 75.3 kHz.According to the design principle of industrial platform,a three-level APF experimental prototype of 380V/60A is built,and the key design parameters of the prototype are given.Relevant experiments such as harmonic compensation are carried out on the experimental prototype to verify the correctness of IP core and parameter design of the experimental prototype.