TNN-based Traffic Sign Recognition Algorithm Design And FPGA Verification

In recent years,the socio-economic development has greatly increased the amount of car ownership,which resulted in the increasingly prominent problems of road traffic safety and traffic congestion.The vehicle-mounted traffic sign recognition system(TSR),as an important component of the driver assistance system,can effectively improve the car safety performance,reduce the incidence of traffic accidents,and alleviate traffic congestion,which has important research values.Common TSR methods are summarized and convolutional neural network algorithms are introduced in this thesis.In view of the large amount of parameters and high computational complexity of convolutional neural networks in practical applications,tensorizing neural network algorithm is used for TSR.Using tensor decomposition to optimize the parameters of the full-connection layer of the convolutional neural network,the number of full-connection layer parameters is reduced by 80%.In this thesis,the convolutional neural network,tensorizing neural network and hardware verification network structure are designed.The GTSRB database is used as the object to train and analyze the three structures.The experimental results show that the tensorizing neural network parameters are 0.93 M,which is 60% of the convolutional neural network.The recognition rate is 97.63%,which is 0.72% lower than that of the convolutional neural network.The hardware verification network parameter is 0.58 M,and the recognition rate is 95.11%.An FPGA verification system and the universal fixed-point neural network convolution accelerator are designed for the algorithm.AXI bus is used for data transmission.ARM and FPGA work together to improve system scalability.This thesis is based on Zynq-FPGA to complete the tensorizing neural network TSR algorithm FPGA circuit design and ARM software design.The system is built to complete the test validation.The test of the system shows that theTSR algorithm occupies 20372 LUT resources(38.29%)on the Zynq-702 N FPGA and the on-chip RAM resources of 2007Kb(79.64%)at a working frequency of 100 MHz for 48?48 input images.The speed of image recognition is 33 frames per second and the recognition rate is 95.11%.The system designed in this thesis has the characteristics of high recognition rate,good real-time performance,small size and high resource utilization rate,which can meet the application requirements.