Development Of A Frequency Agility Demodulation Midfrequency Unit

With the continuous development of science and technology,information warfare gradually replaced the mechanized warfare and became the main form of future war.Compareding with mechanized warfare,the two sides of information warfare contend for information superiority more fiercely,and the electromagnetic environment in the battlefield is more complicated.Therefore,many universities and research institutes at home and abroad have invested a lot of strength and research on high reliability and high security satellite communication system applied to complex electromagnetic environment.This thesis is generated under this background.The main research objective of this thesis is to complete the development of the frequency agility demodulation midfrequency unit,which is an important part of frequency agility communication systems.Compared with common demodulation units,we need to break through the following two key technologies,the hopping speed is greater than 10000h/s and it supports two bands of 50MHz~180MHz& 900MHz~4800MHz simultaneously.These technologies have high practical value,and they are in the leading position in China.The breakthrough of the above technology has great significance to the development of frequency agility satellite communication systems.Before project design,this thesis starts with the principle of PLL,introduced the basic structure of PLL,analyses the main factors affecting phase noise and lock time,and finds methods to improve the above indicators.Then,by comparing the two schemes to achieve FH local oscillator,the realization scheme of FH local oscillator is determined.Next,by analyzing the five architectures of the receiver,the advantages and disadvantages of each architecture are summarized.The form of Zero-IF architecture is chosen as the realization mode of frequency agility frequency conversion unit.Finally,through the analysis of the reasons that affect the demodulation performance of the system in the Zero-IF architecture,the solutions are given.In order to achieve the design goal,the frequency agility demodulation midfrequency unit is devided into two parts: FH local oscillator unit and demodulation midfrequency unit.After the decomposition of the two units about technical indicators,the implementation plan is given in this thesis.Then various drawings are finished with drawing tools Altium Designer and Solid Works.Finally,the feasibility of the scheme is verified by processing test,and the research work is completed.There are two innovations in this thesis.The one is realizing the FH local oscillator of 10000h/s by using two PLLs,continuous switching from a and b,with the help of Qorvo's integrated chip RFFC5072 A.By optimizing the traditional Zero-IF structure of the receiver and adding a frequency conversion at low frequency band,realizing the compatibility of the demodulation midfrequency unit to high and low frequency band,meeting multi band application requirements.Finally,after actual tests,the objectives of this thesis are all completed,even better than expected.