Verilog-A Modeling Of Buck Switching Mode Power Supply

Power supply is a core component of all electronic devices.It‘s quality has an important impact on the stability,security and reliability of electronic supplies.With the rapid development of the electronic information industry,Switch Mode Power Supply(SMPS)as an indispensable power supply mode,it has been continued to look at ways of innovation.Because of its small size,light weight and high efficiency,it can be seen on almost all daily electrical equipments.It has been an indispensable power supply mode for the rapid development of the electronic information industry.Modern electronic device has more and more functions thus more and more complex structures.As a core part,the switch conversion circuit has become the main research object in the field of power supply development.In this thesis,theoretical analysis and simulation studies are carried out on DC-DC Buck switching circuit.Firstly,in this thesis,the switching power supplies are classified according to different working modes.Mainly introduces the basic topology of the Buck switching converter and makes a detailed analysis of it's working principle.Secondly,the system is divided into functional modules through the top-down method.Setting up the high level behavior module of the bandgap voltage reference,analog switch circuit,phase frequency detector,charge pump,voltage controlled oscillator,frequency division devise,phase-locked loop,PWM comparator,transconductance amplifier and RS flip-flop by using verilog-A language.Each module is simulated to verify its function.Finally,a complete switching power supply topology system is built according to the basic structure of the Buck switching power supply.The functional modules which passed the simulation verification are connected in the simulation file.HSPICE software is used to carry out the overall system-level simulation of the circuit.Then,analyzing the correctness of the simulation results and verifies the overall rationality.The thesis carry out the preliminary feasibility analysis by building behavioral model with verilog-A language.The simulation results show that all the indicators meet the design requirements and reach the expected target.Compared to other research methods,not only the simulation time is greatly shortened,but also the flexibility is further improved.