Characterization Of SiC MOSFET’s Switching Oscillations And Device Screening For Paralleled Application

Silicon Carbide(SiC)MOSFET is a promising device for switch mode power electronic converters.The wider bandgap.higher switching speed and higher thermal conductivity makes this device be preferable over Si based devices like Si IGBT and Si MOSFET in high blocking voltage,high temperature and high frequency applications.Application of SiC MOSFET however faces some challenges like high switching ringing and current imbalance when paralleled.Switching oscillations are aggravated by the high switching speed of SiC MOSFET device.Conducted oscillations increase device power losses as well as causing harmonics which have undesirable effects on the power system.Radiated oscillations may cause electromagnetic interference with the communication and control system.Therefore,there is need to understand the triggering mechanism and characterize these oscillations.Besides oscillations,another challenge to SiC MOSFET application studied in this paper is current imbalance among paralleled devices.Device parameters for SiC MOSFETs show significant variability which lead to current imbalance when the devices are paralleled.This may lead to localize heating and subsequently degradation and failure of the devices.This paper reveals triggering mechanism of the oscillations and investigates the influence of various circuit and device parasitic parameters on oscillations triggering.A simple second-order RLC equivalent circuit model is built by analyzing the switching transient process in detail.Turn-off transient ringing and causes of peak growth is determined based on theoretical and simulation analysis.Experimental results also validate this analysis.Concerning device screening for paralleling,spreads of device parameters are first determined by testing the same production batch of SiC MOSFET device products.A machine learning model based on linear regression algorithm is then developed for sorting devices before paralleling.Experimental results show that proposed devices sorting method can effectively minimize transient and steady state current imbalance of paralleled devices.