A 12-bit Low Power Consumption SAR ADC For Implantable ECG Monitoring

The mortality rate of heart disease among all major diseases ranks higher.Raising the rate of diagnosis of sudden clinical diseases such as tachycardia,heartbeat pause,atrial tachycardia,and fibrillation is an effective way to reduce cardiac mortality.In order to monitor heart activity every minute so that patients can be diagnosed and treated in time,implantable electrocardiography(ECG)monitoring has been developed.Implantable ECG monitoring equipment can be implanted under the skin near the heart used to monitor electrical activity,record and transmit abnormal data for helping doctors analyze disease.And the system is mainly composed of battery,wireless transceiver,analog front end(AFE),and a digital signal processing(DSP)and other modules.AFE is made up of a low noise amplifier(LNA)and an analog-to-digital converter(ADC).The ECG signal from electrodes is amplified,filtered,and quantized by AFE.In the actual scene,due to factors such as electrode spacing,electrode noise,and battery life,low power consumption,low noise,and wide dynamic range are required for AFE.Successive-approximation-register(SAR)ADC has a superior power efficiency among all structures of ADCs.Currently the low-power SAR ADC used in ECG acquisition has not more than 10-bit resolution,It does not meet the application requirements of high input dynamic range and high conversion accuracy.Ideally,SAR ADC increases 1-bit in resolution,comparator has to consume 4× power consumption to reduce the noise power thus reducing power efficiency.Besides,it is difficult to achieve 12-bit resolution under low supply voltage because of circuit non-ideal factors such as charge injection,non-linearity of switch on-resistance,and capacitance mismatch.In response to these challenges,a 12-bit SAR ADC with nW-level power consumption,small size,and high resolution is designed by researching on non-ideal factors and ultralow-power technology in circuits.Thus the performance requirements of AFE are met for low-power,low-noise,wide dynamic range.On the one hand,the circuit is designed in terms of system power consumption,dynamic power consumption and static power consumption to reduce the power consumption of ADC.Firstly,a low-duty cycle asynchronous SAR logic technique and a multi-supply voltage technique are proposed to reduce system power consumption.Secondly,in terms of reducing dynamic power consumption,a time-division comparator scheme is proposed,and the MSBs in segment capacitive DAC are thermometer-encoded and inverter switching technique is adopted.Lastly,as reducing static power consumption as concerned,transistors are stacked and high in combination with low threshold transistors are used.On the other hand,it is necessary to reduce the influence of circuit non-ideal factors for example nonlinearity.First,the offset voltage of the time-division comparator is reduced by the offset calibration technique.And then the linearity of the sampling switch is improved by means of a bootstrap circuit technology and dummy transistors are added in order to reduce signal feedthrough and charge injection.The SAR ADC is implemented in TSMC 65 nm CMOS process and occupies an area of 150?m×390?m.At a sampling rate of 1kS/s,it is showed that SNDR is 70.2Db,an ENOB is 11.37-bit and the power consumption is 18 nW when 1V/0.5V supply is applied.Thus a figure-of-merit(FoM)is 6.8fJ/conv.step.In the whole,the designed SAR ADC has achieved low power consumption,high-resolution and small area.