Design Of A Low Power Dual Slope ADC For Wireless ECG Signal Measurement

"China’s cardiovascular disease report 2016"pointed out that China’s current number of cardiovascular disease patientshas reached 290 million,and the prevalence and mortality of cardiovascular disease is still in the ascendant phase,cardiovascular mortality accounted for more than 40%of the deaths.Therefore,the prevention of cardiovascular diseases has become particularly important.Electrocardiogram(ECG)is an important measure for monitoring cardiovascular conditions,and generally ECG measurements can only be carried out in professional institutions such as hospitals.As people pay more and more attention to health issues,the demand for portable ECG measurement devices is rising.This thesis focuses on the design of a dual slope analog-to-digital converter(ADC)in a wirelessly powered ECG measurement system.Firstly,this paper introduces the architecture of the wirelessly powered ECG measurement system,and summarizes the requirements of the system structure and performance of the ADC.From the perspective of low power consumption and transient current reduction,we decided to use a dual slope ADC.Then various structures of the dual slope ADC were investigated.The error caused by the parasitic capacitances of the resistors was analyzed,and in order to eliminate the influence of the parasitic capacitance,the switched capacitor integrator is adopted and the method of alternating integration is used.This new method greatly reduces the area of the integrating capacitor and also reduces the effect of the comparator offset on the ADC output.The sub-module of the ADC is described in detail,including sample and hold circuit,integrator,auto-zero circuit and so on.Finally,the layout of the chip and post-layout simulation is presented.The proposed 10-bit dual slope ADC consums 18.5-μA current with a sampling rate of 418S/s at 2-V supply voltage.The proposed dual slope ADC is implemented in 0.35-μm CMOS process occupying an area of 0.16mm~2.Pre-simulation results show that the effective number of bits(ENOB)for the ADC is 9.43 bits.