Time Domain Analysis And Decoupling Design Of Power Distribution Network Voltage Noise

Along with the rapid development of integrated circuits,the internal clock frequency of high-speed digital systems continues to rise,the current transient amplitude and speed gradually increase,and the supply voltage continues to decrease,which makes the voltage noise amplitude larger and the absolute tolerance decreases.Therefore,it is significant to accurately evaluate voltage noise and develop an effective power distribution network decoupling scheme for ensuring the efficiency of the high-speed digital system.At present,the PDN design technique based on the frequency domain target impedance method is a representative method for evaluating the quality of PDN design in the industry.The problem with this technique is that the description of impedance in high-frequency region is not accurate,which resulting in over-design of the PDN.Although the PDN time domain design can reflect the voltage noise more precisely with the analytic formula,the typical lumped circuit model in the design needs to establish the 2n-order differential equation after n-level cascade,and it is impossible to directly calculate the time-domain analytical formula of voltage noise.In addition,the design of the decoupling network from the lumped circuit model ignores the distributed effect of the circuit design at high frequencies,especially the influence of the loop inductance affected by the layout position of the capacitor components on the circuit in the high-frequency region.On the basis of the above problems,this paper firstly introduces the structure of PDN and the common decoupling design methods.On this basis,the complex board-level PDN lumped circuit model is derived,and then reasonable equivalent simplification is made to make it possible to solve the temporal noise analytical formula.Then,using the step current with rising edge as the input current excitation source,the voltage noise time domain analytical formula with one or more decoupling capacitor branches is derived theoretically.Analyze the time domain analytical equation to get the pattern of voltage noise fluctuation,which is the relationship between voltage noise maximum,time,voltage noise maximum and rise time.According to this pattern,a decoupling capacitor selection scheme of VRM level,bulk capacitance level and surface mount capacitance level is developed.According to the relationship between the capacitance capacity and the sensitivity of the loop inductance,the layout principle of placing the decoupling capacitor and the small capacitance of the capacitor close to the noise source is given.Finally,an optimized capacitor layout algorithm based on the distance of the noise source and the capacitance value is proposed.Through the simulation of Matlab software,it is verified that the absolute error of the power distribution network equivalent simplification method does not exceed 10%,and the maximum of time domain analytic calculation of the voltage noise match with the ADS simulation results.In the ADS,the decoupling capacitor selection method based on voltage and noise time domain analysis is validated to suppress the voltage noise fluctuation.It shows that this simplified method and the decoupling capacitor selection method are authentic,effective and practical.The simulation comparison using Cadence software verifies the rationality of placing small capacitors around the noise source and the overall layout of the decoupling capacitors closer to the noise source is reasonable.The layout optimization algorithm can quickly and effectively lay out the positions of the selected capacitors,so that the capacitance of each magnitude can exert a good decoupling effect.In general,This paper successfully overcomes the over-design problem of frequency domain design and improves the description accuracy of voltage noise.The decoupling design of voltage noise proposed in this paper provides a new idea for solving the problem of power distribution network design,saving design resources and cost,and has certain reference value and practical significance for PDN time domain design.