Research On Modeling And Suppressing Of Common Mode Emi For Three-level Active Neutral Point Clamped Inverters

SiC devices can upgrade the inverter performance to a new level by its potentially more than 10 times higher switching speed compared to its Si counterpart.Whereas,the high switching frequency and dv/dt,di/dt worsen the electromagnetic interference(EMI).Reduction of the common mode(CM)noise of the non-isolated photovoltaic(PV)inverters are addressed by many researchers through adding filters or balancing the circuit.However,most methods rely on the certainty of the parasitics in the system in advance.It is usually not practical for a PV inverter because the parasitic capacitance of PV panels that are to be installed in plants varies from case to case and further can be seriously affected by the damp environment.This paper proposes a practical way to reduce the CM noise of the 3-level(3L)active neutral point clamped(ANPC)inverters with uncertain parasitic capacitance of PV panels.Firstly,the CM model of ANPC inverters with all parasitic capacitances is established.Next,most existing hardware-based reduction methods of the CM noise are summarized based on a unified mathematical model and further compared with each other.After the comparison,a practical method is proposed to reduce the CM noise of the ANPC inverter with uncertain parasitic capacitances,which just adds little volume and cost to the whole system.Finally,the simulation and experiments are conducted to validate the proposed method.The impedance balance technique is a good way to reduce the CM noise by making the voltage across the LISN as small as possible.However,a side effect of this technique is the generation of relatively large loop current that circulates in the inverter.It can cause additional losses and cost,which can be a factor that stops the increase of the switching frequency by Si C MOSFET.This paper,for the first time,analyzes the relationship between the CM noise and loop current of 3-level ANPC inverters and proposes a co-reduction method for both.Firstly,the CM noise and loop current are clarified for the ANPC inverters.And,both analytical models are established.The relationship and how they conflict with each other are then addressed.Based on this,possible actions are proposed to both reduce the CM noise and loop current and guidelines are given for practical design.Finally,the proposed technique is verified by simulation and experiment.