Application Of Large-capacity Storage In Oscilloscope Power Analyzer

With the increasing consumption of global energy and increasing attention to power efficiency,engineers must conduct rigorous test and measurement in the design of power electronics application systems to obtain accurate data to help them achieve their design goals.For applications such as power control devices,battery management systems,inverters,etc.that require high power efficiency,it is often necessary to capture and analyze transient abnormal signals.The large-capacity storage oscilloscope power analyzer is a multi-channel high-precision measurement instrument that combines traditional power meters,traditional oscilloscopes,and recorders,and can well meet the needs of engineers for such test and measurement.Mass storage on the one hand means that more data can be stored,on the other hand it means that more channels of data can be stored simultaneously.Based on the project of an oscilloscope power analyzer,this paper conducts relevant research on the storage and transmission structure of the oscilloscope power analyzer.This paper proposes a large-capacity storage framework for the storage requirements of modules with multiple channels and different sampling rates.The framework adopts a hierarchical and modular design idea.The AXI4 bus is used as the interconnection protocol between each module,which simplifies the storage and transmission of data.By using the XDMA framework to bridge the PCIe protocol on the host side and the AXI protocol on the FPGA side,the host computer can perform register configuration and mass data movement through PIO mode and DMA mode,respectively.The AXI4 bus is used to interconnect the logic modules in the FPGA board.It not only meets the requirements of data transmission rate matching between different systems,but also satisfies the data transmission exchange between various modules in the signal processing board.For the deep storage,rolling storage,data recording and dual capture functions of the oscilloscope power analyzer,this article adopts a modular design.By distinguishing the common part and characteristic part of these functions,a general storage mode is designed for the common part storage And trigger storage mode,a variety of module functions are designed for the characteristic part.For the data recording function and the rolling storage function,the data is cached in the off-chip storage particles by adopting a ping-pong operation pipeline design to ensure real-time data recording.This design uses DDR3 memory particles with an external capacity of 512 MB,divided into 4 channels.It can realize the storage of up to 16 Mpts in a single channel.This framework can be time-division multiplexed to achieve up to 4 deep storage,2 rolling storage,2 data recording and 2 dual capture functions.After the final test and verification,the storage subsystem architecture designed in this paper fully meets the design requirements...