Design Of Dual-Output DC-DC Converter With Constant On-Time Control

Power management chips have a very important position in electronic equipment.It has absolute advantages in terms of the accuracy of the power supply voltage,the ability to drive the load,the fast response of the power supply,and the power density.The valley current mode constant on time(Constant On Time,COT)controlled Buck converter has higher light load efficiency due to its variable frequency operation characteristics,and is often used in low load environments.The transient response speed of COT is fast,and the overshoot is small.Therefore,based on the dual-channel valley current mode COT-controlled Buck converter chip,this dissertation proposes new research ideas and solutions for its two major challenges-high switching frequency and high stability.1.High switching frequency: The higher switching frequency brings many challenges to the circuit design,and the time delay of the control circuit is one of the important factors.Delays in circuit modules such as comparators and drivers are unavoidable,which has an adverse effect on the control of high-switching frequency converters.However,it has not been analyzed in existing small-signal models.Therefore,this dissertation establishs a corresponding model for the time delay phenomenon by the Describe Function(DF)model method,which performs simulation verification through Simplis and analyzes the effect of time delay on the system loop,and gives the Time delay margin for the high-frequency converter.Under the guidance of this model,a high switching frequency valley current mode Buck converter chip is designed through the 0.18μm BCD process.The chip’s benchmark can achieve 1%accuracy in the full temperature range,and the important functions such as power-on,maximum load capacity and load step ability are normal,its load regulation rate is less than five thousandths,and the frequency is high to 4MHz.2.High stability: the dual-channel converter has an on-chip coupling path,which will cause cross interference between the converters.In addition,low output voltage and low sampling resistance will cause the slope of the current ramp to decrease,and the ability to resist noise is insufficient,causing jitter and even oscillation.The common solution is addingfixed slope for compensation.This dissertation analyzes the advantages and disadvantages of the technology,and analyzes the limitations of the transient response introduced by the slope by establishing a small signal model.In orderto improve the stability of the converter,an adaptive slope compensation technique is proposed.In this technique,the output voltage and feedback voltage information are added into the loop to adjust the slope of the ramp.The difference between the feedback and the reference forms a current to control the ramp,which changes the slope during transients,quickly adjusting the duty cycle.On the other hand,the output voltage information is used to generate current to adjust the steady-state value of the ramp.Based on this idea,this dissertation built a Buck circuit with a phase-locked loop dual output constant on-time control.Its input voltage range is 3.6V-20 V,which outputs two signals with opposite phases at the same time.The maximum output current of the channel is 3A.The typical frequency is 1MHz.The adjustable switching frequency range is 500kHz-4MHz in the operating temperature which is-50 ℃~150 ℃.The maximum efficiency is high to 96%,and it can keep a high efficient when the load is very low.On the 0.18μm BCD process,complete sub-module scaffolding and sub-module simulation,as well as the construction of the overall architecture and simulation verification of the chip.