Modelling And Design With Several Modules Of Configurable Application-Special Processor

Hardware-Software co-design is a hot topic in SoC developing field which parallels the software and hardware development by top-level design with the system model,hardware-software partitioning,system-level co-simulation.This technology can accelerate the system development,decrease the error rate,shortening time and lower cost.This paper researches the mothod and procedure of hardware-software co-design and gives a transaction level module of configurable application-specific processor.The modelling language and object,the mode of operation and main modules are introduced gradually.The cycle-accurtion model is created by adding timing information to function module.The paper studies the cycle-accurate module of FFT and sorting and the hardware implementation of the sorting.First of all,according to the algorithm and computing resource,a parameterized configurable cycle-accurate module of FFT is implemented.The mixed-Radix8 FFT,4 parallel computation and memory architecture-based design are used in this model which based on the research of the hardware implementation architecture.The module is build with Ping-Pong structure and can work in debugging mode.In the following chapter,a parameterized configurable cycle-accurtion module of sorting is implemented.The morge sort,2 parallel computation and architecture with 2 single floating-point adder are used in sort hardware accelerator based on algorithm,computing and memory resource.In the part of simulation and verification,the paper researches the method and procedure of Hardware-Software co-simulation and show the test result.In the simulation,the module achives the cycle accu rate and is simulated 30 times faster than the hardware at 65536 points and 72 times faster than the hardware at 524288 points,which shows the advantage of the module.The sort hardware accelerator implements the 128k single floating-point parallel soring.The accelerator calculate 2048 numbers in 330 μs and calculate 16000 numbers in 2800 μ s at 123.6MHz.It also gives the simulation waveforms and test result which achieves the preset indicators.