Polymer Field-effect Transistors With Low/High Dielectric Constant Polymer Bilayers As Gate Insulating Layers

Researchers in the field of organic field-effect transistors(OFETs)usually focus on organic semiconductor materials with high mobility,high stability,and easy solution processing.With the development of scientific research,researchers have found that gate insulating layers play a key role in the performance of OFET devices.They influence the transport of carriers through directly affecting the molecular arrangement of the upper semiconductor material and determining the insulating/semiconductor interface quality.An ideal dielectric material for high device performances should possess high capacitance,low leakage current,low interfacial density of trap states,and good compatibility with an organic semiconductor.However,a single-layer gate dielectric cannot meet the requirements.To address this problem,bilayer gate dielectrics,consisting of a low-k dielectric in contact with an active layer and an underneath high-k insulator,have been utilized for controlling interface properties and improving the performances of OFETs This paper mainly explores the interface between insulation layer and insulator/semiconductor layer through two parts.(1)In bottom-gated organic field-effect transistors(OFETs)carrier transport and device performances show strong dependencies on the dielectric and surface properties of gate insulating materials.The single insulating layer is difficult to meet the requirements of large capacitance and low interface polarity at the same time,thus,a low k/high k bilayer which was composed of weak polar poly(vinyl phenol)(CL-PVP)and strong polar polyvinyl alcohol(PVA)was designed as dielectric layer.The high performance field-effect transistors were prepared and studied with poly(3-hexyl thiophene)(P3HT)as the active layer.The performance of the device with double insulation layer is obviously higher than that of CL-PVP and PVA.The mobility,threshold voltage and on/off current ratio are 0.1 cm2 V-1 s-1,5 V and 103.The charge trap density,value of 8.4 ×1012 cm-2 eV-1,was calculated by the subthreshold swing(5 V/dec).(2)The CL-PVP/PVA bilayer shows that low k/high k dielectric layer can effectively improve the performance of the device.However,the hysteresis of the device still exists because of the weak polarity of CL-PVP.Therefore,the weaker polarity cross-linked poly(methyl methacrylate)(CL-PMMA)and the strong polarity PVA are used to form CL-PMMA/PVA bilayers to further reduce the hysteresis.The surface and electrical properties of the insulating layer were studied.The surface roughness increases from 0.386 nm to 0.532 nm,and the capacitance drops to 11.5 nF/cm2 from 14.2 nF/cm2 by the cross linking,however,the contact angle of water is greatly raised from 36° to 68°,indicating that the surface polarity of PVA is remarkably decreased by adding CL-PMMA.Additionally,the leakage current of the CL-PMMA/PVA layer is reduced by about 2 orders of magnitude.The field-effect transistors were built with P3HT as active layer.The performance of the device with the CL-PMMA/PVA insulating layer is significantly improved,with the on/off ratio increased reaching～102 and 3.3×10-2 cm2 V-1 s-1,respectively.Furthermore,the hysteresis of the P3HT-OFETs has been reduced dramatically.The hysteresis was further studied by the C-V curve.It is found that the hysteresis is related not only to the polarity of the active layer/insulator interface,but also to the polarity of the insulation layerThe results demonstrate that the polymeric materials pair made up of low k and high k dielectrics enhance the total performance of OFETs and are the promising gate layer for high-performance PFETs.