Design Of Low-noise High-sensitivity 64×64 Readout Circuit For Infrared InGaAs Focal Plane

With the development of infrared technology,shortwave infrared In Ga As focal plane detectors are more and more widely used in aerospace,military,civil inspection and other fields.In recent years,the performance of infrared In Ga As focal plane arrays has been continuously improved while the level of dark current has been declining.In Ga As focal plane detectors have shown great potential for imaging in low-light night-vision environments.It is important to improve the sensitivity of In Ga As focal plane detector and restrain the noise of the detector readout circuit from imaging the detector under low light conditions.The application background and development status of shortwave infrared In Ga As focal plane detector are introduced.Its composition and working principle are introduced.The composition and working principle of 64×64 element readout circuit in focal plane are introduced,and the noise of readout circuit is analyzed.Design a focal plane with 64×64 yuan readout circuit.Thesis work as follows:1.The input stage is the main source of 64×64 readout circuit noise.In order to restrain the input stage noise of the readout circuit,a single-ended operational amplifier is used to make the integral amplifier of the input stage,thereby reducing the number of MOS transistors in the op amp.,to suppress the thermal noise of the integrated op amp.A small capacitor is used to the integrated capacitance of the input stage of the readout circuit to suppress the correlated noise caused by the integral capacitor.The integrated capacitor is 1f F to 10 f F for comparative observation.64×64 readout circuit overall power consumption as low as 9.01 m W,and 1f F readout circuit noise is 5.18 e.2.Using a small integral capacitor can not only suppress the noise of the readout circuit,but also can improve the sensitivity of the focal plane detector.Compared with MOS capacitor,MIM capacitor,MOM capacitor characteristics and advantages,considering the layout process uniformity and circuit requirements,the use of MOM capacitor to do a small integral capacitance of readout circuit.3.The 0.18 ?m process is used to design a 64×64 readout circuit for In Ga As focal plane,including input stage,correlated double sampling circuit,output stage,column-shift register,row-shift register,column buffer,column buffer switch and bus buffer.The timing of shift register,reset switch and sampling switch are designed and the simulation result is correct.Completed the overall layout of the 64×64 readout circuit layout,and the layout is verified by DRC,LVS detection and PEX parameters extraction of the MOM capacitor and the tape is sent out.