Design Of High Performance Reconfigurable Floating Point General Purpose Coprocessor

With the progress of the times,the environment faced by technology products has become complex and changeable,the traditional general-purpose processors and application-specific integrated circuits are difficult to achieve the demand for high performance and high flexibility.Due to the high ratio of energy efficiency,rich computing resources,and flexible interconnections.Reconfigurable processors have been widespread concern.At the same time the rapid development of integrated circuit technology and computer technology,made the multi-core SoC(System on Chip,SoC)came into the eyes of researchers.The direction of development has gradually changed from the pursuit of higher single-core frequency to the pursuit of more processor cores.NoC(Network on Chip,NoC)apply parallel computing technology and computer networks in the chip,which has advantages in terms of bandwidth,scalability and reliability and has become the mainstream of on-chip Internet.At the same time,the requirements for data processing accuracy and real-time performance in speech signal processing,graphic display,scientific computing and other research fields are getting higher and higher.Most hardware systems need have strong floating-point calculate ability.Based on the multi-core system architecture of the research group,general-purpose processor,application specific integrated circuit,on-chip network technology and reconfigurable technology,this paper designs a dynamic reconfigurable floating-point processor mainly for high-density computing.and a dynamic reconfigurable floatingpoint processor is used as a resource computing node to construct a homogeneous multicore system which has been loaded typical algorithm tasks to test its performance and parallelism.The main work of this paper is as follows:First of all,this paper introduced the multi-core system architecture and on-chip network structure.According to the algorithm tasks and functional requirements loaded in multi-core system,the overall architecture of dynamic reconfigurable floating-point processor is determined.In order for the application of data-intensive and computeintensive algorithms,the reconfigurable floating-point processor is compatible with both storage and streaming modes to maximize computational efficiency and algorithm adaptability.At the same time the reconfigurable floating-point processor add pulsation mode to achieve a compromise between flexibility and work efficiency.Secondly,the specific structure and working mechanism of microcontroller unit,function configuration unit,memory management unit and network interface unit in reconfigurable floating-point processor are introduced,and a mathematical model is proposed,which can help optimize the interconnection between computing units.Finally,a verification platform is built for the reconfigurable floating-point processor,and the correctness of its functions is verified by loading vector calculation tasks.The homogeneous multi-core system with appropriate network size is constructed.The computational efficiency and algorithm adaptability of reconfigurable floating-point processor in multi-core system are verified by loading FFT algorithm.